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    PROGRAMMABLE LOGIC INTEGRATED CIRCUIT
    2.
    发明申请
    PROGRAMMABLE LOGIC INTEGRATED CIRCUIT 有权
    可编程逻辑集成电路

    公开(公告)号：US20170070228A1

    公开(公告)日：2017-03-09

    申请号：US15122433

    申请日：2015-02-27

    Applicant: NEC Corporation

    Inventor： Ryusuke NEBASHI ,  Makoto MIYAMURA ,  Noboru SAKIMURA ,  Yukihide TSUJI ,  Ayuka TADA

    IPC: H03K19/177 ,  G11C29/00 ,  H03K19/173

    CPC classification number: H03K19/17736 ,  G11C29/86 ,  H03K19/1736 ,  H03K19/1776

    Abstract: In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires.

    Abstract translation: 在可编程逻辑集成电路中，提供备用电路以准备故障元件的出现导致冗余电路配置。 根据本发明的可编程逻辑集成电路具有：多个逻辑块; 用于通过用于切换的非易失性开关元件来切换行和列线之间的连接的开关块; 以及用于将输入/输出线连接到所述开关块的移位块。 移位器块包括冗余线，并且配备有用于移位的非易失性开关元件，用于控制构成所述冗余线和所述行线的线的连接。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER SUPPLY CONTROL METHOD THEREFOR
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER SUPPLY CONTROL METHOD THEREFOR 有权
    半导体集成电路及其电源控制方法

    公开(公告)号：US20160077563A1

    公开(公告)日：2016-03-17

    申请号：US14786453

    申请日：2014-01-07

    Applicant: NEC CORPORATION

    Inventor： Yukihide TSUJI ,  Noboru SAKIMURA ,  Ryusuke NEBASHI ,  Ayuka TADA

    IPC: G06F1/26 ,  G06F13/40

    CPC classification number: G06F1/3287 ,  G06F1/3209 ,  G06F1/3243 ,  G06F13/4022 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

    Abstract: A semiconductor integrated circuit (100) comprising: a plurality of processing circuits (11, 12, 13) each including a notification units for outputting a notification signal according to the processing state of the own processing circuit; a plurality of power supply switch units (SW1, SW2, SW3) for switching the connection states between the respective processing circuits and a power supply source; a power supply switch control circuit which is connected with the notification means (111, 121, 131), stores power supply control information (101) including a plurality of connection statuses, and controls the connection states on the basis of the notification signals and the power supply control information; and a data bus (BS) and the like connecting each of the processing circuits and the power supply switch control circuit, wherein: at least two or more of the plurality of processing circuits update the power supply control information via the data bus and the like before outputting a notification signal; and the power supply switch control circuit accepts a notification signal outputted from any one of the plurality of processing circuits after the update, and accordingly controls the connection states of respective ones of the plurality of power supply switch units on the basis of the updated power supply control information.

    Abstract translation: 一种半导体集成电路（100），包括：多个处理电路（11,12,13），每个处理电路包括根据本处理电路的处理状态输出通知信号的通知单元; 用于切换各个处理电路和电源之间的连接状态的多个电源开关单元（SW1，SW2，SW3） 与通知装置（111,121,131）连接的电源开关控制电路存储包括多个连接状态的电源控制信息（101），并且基于通知信号来控制连接状态， 电源控制信息; 以及连接处理电路和电源开关控制电路中的每一个的数据总线（BS）等，其中：多个处理电路中的至少两个或更多个通过数据总线等来更新电源控制信息 在输出通知信号之前; 并且电源开关控制电路接受在更新之后从多个处理电路中的任一个输出的通知信号，并且因此基于更新的电源来控制多个电源开关单元中的各个电源开关单元的连接状态 控制信息。

    PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND CHARACTERIZATION METHOD
    4.
    发明申请
    PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND CHARACTERIZATION METHOD 审中-公开

    公开(公告)号：US20190052273A1

    公开(公告)日：2019-02-14

    申请号：US15752330

    申请日：2016-08-31

    Applicant: NEC Corporation

    Inventor： Ayuka TADA ,  Noboru SAKIMURA ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ryusuke NEBASHI ,  Xu BAI ,  Toshitsugu SAKAMOTO

    IPC: H03K19/177 ,  G06F17/50 ,  H01L27/24 ,  H01L45/00

    Abstract: An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.

    CROSSBAR SWITCH TYPE MEMORY CIRCUIT, LOOK-UP TABLE CIRCUIT, AND PROGRAMMING METHOD
    7.
    发明申请
    CROSSBAR SWITCH TYPE MEMORY CIRCUIT, LOOK-UP TABLE CIRCUIT, AND PROGRAMMING METHOD 审中-公开

    公开(公告)号：US20180096724A1

    公开(公告)日：2018-04-05

    申请号：US15550463

    申请日：2016-03-01

    Applicant: NEC Corporation

    Inventor： Makoto MIYAMURA ,  Noboru SAKIMURA ,  Yukihide TSUJI ,  Ryusuke NEBASHI ,  Tadahiko SUGIBAYASHI

    IPC: G11C13/00 ,  H01L27/24

    CPC classification number: G11C13/004 ,  G06F7/00 ,  G06F7/544 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/12015 ,  G11C29/50008 ,  G11C29/52 ,  G11C2013/0073 ,  G11C2029/5004 ,  G11C2213/75 ,  H01L27/2445 ,  H01L27/2481

    Abstract: In order to provide a crossbar switch type memory circuit designed to be usable in normal circumstances even when a resistance change element is in an adverse state, the present invention is provided with: a first unit including a first column wiring to which one end of a first resistance change element is connected, a first power supply-side transistor for controlling the connection of the first column wiring and a power supply node, a first ground-side transistor, of a reverse operation type to the first power supply-side transistor, for controlling the connection of the first column wiring and a ground node, and a first polarity control line for causing the first power supply-side transistor or the first ground-side transistor to turn on and the other to turn off by a polar signal from a polar signal terminal, the first polarity control line being connected to the control terminals of the first power supply-side transistor and first ground-side transistor; a second unit including a second column wiring to which one end of a second resistance change element is connected, a second power supply-side transistor, of the same operation type as the first power supply-side transistor, for controlling the connection of the second column wiring and the power supply node, a second ground-side transistor, of a reverse operation type to the second power supply-side transistor, for controlling the connection of the second column wiring and the ground node, a logic inversion circuit for inverting the polarity of the polar signal from the polar signal terminal and outputting the polarity-inverted signal, and a second polarity control line for causing the second power supply-side transistor or the second ground-side transistor to turn on and the other to turn off by a polar signal from the logic inversion circuit, the second polarity control line being connected to the control terminals of the second power supply-side transistor and second ground-side transistor; and n row wirings (n: positive integer) to which the other ends of the first and second resistance change elements are connected.

    CONTENT ADDRESSABLE MEMORY CELL AND CONTENT ADDRESSABLE MEMORY
    9.
    发明申请
    CONTENT ADDRESSABLE MEMORY CELL AND CONTENT ADDRESSABLE MEMORY 审中-公开
    内容可寻址存储单元和内容可寻址存储器

    公开(公告)号：US20160300614A1

    公开(公告)日：2016-10-13

    申请号：US14392273

    申请日：2014-06-17

    Applicant: NEC CORPORATION

    Inventor： Ryusuke NEBASHI ,  Noboru SAKIMURA ,  Tadahiko SUGIBAYSHI

    IPC: G11C15/02

    CPC classification number: G11C15/02 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C15/046

    Abstract: In order to provide a technique for reducing an area of a content addressable memory cell and suppressing a leak current in a content addressable memory which calculates similarity, a content addressable memory cell of the present invention, comprising: a resistance network which includes plural current paths, a logic circuit for selecting a current path in response to input data, and a variable-resistance-type non-volatile memory element that is arranged on at least one current path and stores data and whose resistance value is changed according to a result of logical calculation based on the input data and the stored data; and a charge/discharge circuit which is connected with the resistance network and a match line and whose delay time from inputting a signal through the match line until outputting the signal is changed according to the result of logical calculation based on the input data and the stored data.

    Abstract translation: 为了提供减少内容可寻址存储单元的面积并抑制计算相似度的内容可寻址存储器中的泄漏电流的技术，本发明的内容可寻址存储单元包括：电阻网络，其包括多个电流路径 ，用于响应于输入数据选择电流路径的逻辑电路，以及可变电阻型非易失性存储元件，其设置在至少一个电流路径上，并存储数据，并且其电阻值根据 基于输入数据和存储数据的逻辑计算; 以及与电阻网络和匹配线连接的充电/放电电路，其根据输入数据和存储的逻辑计算结果改变从输入信号到匹配线直到输出信号的延迟时间 数据。

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