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公开(公告)号:US20140287557A1
公开(公告)日:2014-09-25
申请号:US14295699
申请日:2014-06-04
Applicant: NICHIA CORPORATION
Inventor: Takuya NOICHI , Yuichi OKADA
IPC: H01L21/48
CPC classification number: H01L21/4853 , H01L23/49582 , H01L23/49811 , H01L23/49827 , H01L24/83 , H01L33/54 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/83 , H01L2924/12041 , H01L2924/12042 , H01L2924/15787 , H01L2924/014 , H01L2924/00
Abstract: In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti.
Abstract translation: 在包括半导体元件和其上安装有半导体元件的布线基板的半导体器件中。 布线基板包括绝缘基板和形成在绝缘基板中并与半导体元件电连接的导电布线。 导电布线包括形成在绝缘基板上的下层,形成在下层上的主导电层和覆盖下层和侧表面的侧表面的电极层和主导电层的上表面。 下层包括形成为与绝缘基板接触并且含有Ti合金的粘附层。
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公开(公告)号:US20130313695A1
公开(公告)日:2013-11-28
申请号:US13900730
申请日:2013-05-23
Applicant: NICHIA CORPORATION
Inventor: Takuya NOICHI , Yuichi OKADA
IPC: H01L23/495 , H01L23/00
CPC classification number: H01L21/4853 , H01L23/49582 , H01L23/49811 , H01L23/49827 , H01L24/83 , H01L33/54 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/83 , H01L2924/12041 , H01L2924/12042 , H01L2924/15787 , H01L2924/014 , H01L2924/00
Abstract: In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti.
Abstract translation: 在包括半导体元件和其上安装有半导体元件的布线基板的半导体器件中。 布线基板包括绝缘基板和形成在绝缘基板中并与半导体元件电连接的导电布线。 导电布线包括形成在绝缘基板上的下层,形成在下层上的主导电层和覆盖下层和侧表面的侧表面的电极层和主导电层的上表面。 下层包括形成为与绝缘基板接触并且含有Ti合金的粘附层。
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