公开(公告)号：US20160261339A1

公开(公告)日：2016-09-08

申请号：US15157189

申请日：2016-05-17

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Kei KITAMURA ,  Kenji HISADOME ,  Mitsuhiro TESHIMA ,  Yoshiaki YAMADA ,  Osamu ISHIDA

IPC: H04B10/032 ,  H04J3/16 ,  H04Q11/00

CPC classification number: H04B10/032 ,  H04J3/1652 ,  H04J3/1664 ,  H04J2203/0094 ,  H04L45/245 ,  H04L45/28 ,  H04L45/745 ,  H04L47/2433 ,  H04L47/34 ,  H04L47/745 ,  H04L47/805 ,  H04L49/552 ,  H04Q11/0005 ,  H04Q11/0062 ,  H04Q11/0066 ,  H04Q2011/0045 ,  H04Q2011/0081 ,  H04Q2011/0083 ,  H04Q2011/0086

Abstract: A multilane transmission device that transmits data frames by using a plurality of lanes, comprising: a data frame allocating unit that allocates data frames based on a transmission destination; a flow group information sequence information adding unit that adds flow group information indicating a flow group corresponding to a transmission source and transmission destinations and sequence information indicating a sequence of the data frames to the data frames allocated based on each transmission destination by the data frame allocating unit; and a lane selecting/outputting unit that transmits the data frames having the respective flow group information and the respective sequence information added thereto by the flow group information sequence information adding unit to the transmission destinations by using one or more lanes corresponding to the respective flow group information.

Abstract translation: 一种通过使用多个通道发送数据帧的多路传输装置，包括：数据帧分配单元，其基于发送目的地分配数据帧; 流量组信息序列信息添加单元，其通过数据帧分配将表示对应于发送源的流组的流组信息和发送目的地以及指示数据帧序列的序列信息添加到基于每个发送目的地分配的数据帧 单元; 以及车道选择/输出单元，其通过使用与各个流动组对应的一个或多个车道将具有各个流动组信息和由流动组信息序列信息添加单元附加的各个顺序信息的数据帧发送到发送目的地 信息。

公开(公告)号：US20180175830A1

公开(公告)日：2018-06-21

申请号：US15553909

申请日：2017-01-16

Applicant: NTT ELECTRONICS CORPORATION ,  NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Yasuharu ONUMA ,  Etsushi YAMAZAKI ,  Kazuhito TAKEI ,  Osamu ISHIDA ,  Kengo HORIKOSHI ,  Mitsuteru YOSHIDA ,  Yoshiaki KISAKA ,  Masahito TOMIZAWA

IPC: H03H17/02 ,  H04L7/00

CPC classification number: H03H17/0227 ,  H03H17/0213 ,  H03H17/0275 ,  H03H17/0685 ,  H03H2017/0214 ,  H03H2017/0245 ,  H03H2017/0247 ,  H03H2017/0298 ,  H04L7/0029 ,  H04L7/005 ,  H04L7/0087

Abstract: A parallel transfer rate converter inputs first parallel data with number of samples being S1 pieces in synchronism with a first clock, and outputs second parallel data with number of samples being S2=S1×(m/p) pieces (p is an integer equal to or larger than 1) in synchronism with a second clock having a frequency which is p/m times of a frequency of the first clock. A convolution operation device inputs the second parallel data in synchronism with the second clock, generates third parallel data with number of samples being S3=S2×(n/m) pieces (S3 is an integer equal to or larger than 1) by executing a convolution operation with a coefficient indicating a transmission characteristic to the second parallel data, and outputs the third parallel data in synchronism with the second clock.

公开(公告)号：US20180152247A1

公开(公告)日：2018-05-31

申请号：US15575286

申请日：2016-09-05

Applicant: NTT ELECTRONICS CORPORATION ,  NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Osamu ISHIDA ,  Etsushi YAMAZAKI ,  Kazuhito TAKEI ,  Masahito TOMIZAWA ,  Hideki NISHIZAWA

IPC: H04B10/516 ,  H04B10/40 ,  H04B10/60

CPC classification number: H04B10/516 ,  H04B10/40 ,  H04B10/50 ,  H04B10/60

Abstract: Signal processing sections selectively switch modulation/demodulation in low-efficiency modulation system and modulation/demodulation in high-efficiency modulation system, and perform digital signal processing. Parallel-side interfaces of input/output interface sections are electrically connected to the signal processing section. A serial-side interface of the input/output interface section is electrically connected to a serial-side interface of the input/output interface section. A selection section electrically connects a parallel-side interface of the input/output interface section to the signal processing section when the low-efficiency modulation system is selected, and electrically connects the parallel-side interface of the input/output interface section to a parallel-side interface of the input/output interface section when the high-efficiency modulation system is selected.

公开(公告)号：US20180068095A1

公开(公告)日：2018-03-08

申请号：US15551691

申请日：2016-03-03

Applicant: NTT Electronics Corporation ,  NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Etsushi YAMAZAKI ,  Osamu ISHIDA ,  Kazuhito TAKEI ,  Yasuhiro SUZUKI ,  Hideki NISHIZAWA

IPC: G06F21/12 ,  H04B10/27 ,  H04B10/40

CPC classification number: G06F21/12 ,  G06F21/10 ,  G06F21/71 ,  G06F2221/0704 ,  H04B10/27 ,  H04B10/40 ,  H04L12/28 ,  H04L41/00

Abstract: A processing equipment includes a processing unit having a plurality of functions. A retaining unit retains a device identifier capable of identifying the processing equipment. An interface unit receives a function authentication key which is a code for setting a specific function among the plurality of functions to be enabled or disabled. A control unit sets the specific function to be enabled or disabled according to the function authentication key when a device identifier included in the received function authentication key coincides with the device identifier retained in the retaining unit.