公开(公告)号：US11558064B2

公开(公告)日：2023-01-17

申请号：US17616643

申请日：2020-01-07

申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION ,  CHONGQING GIGACHIP TECHNOLOGY CO. LTD.

发明人： Daiguo Xu ,  Hequan Jiang ,  Ruzhang Li ,  Jianan Wang ,  Guangbing Chen ,  Yuxin Wang ,  Dongbing Fu ,  Liang Li ,  Yan Wang

IPC分类号： H03M1/12 ,  H03M1/46

摘要： SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.

公开(公告)号：US11942963B2

公开(公告)日：2024-03-26

申请号：US17921990

申请日：2021-01-19

申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION ,  Chongqing GigaChip Technology Co., Ltd.

发明人： Daiguo Xu ,  Dongbing Fu ,  Zhengping Zhang ,  Zhou Yu ,  Jian'an Wang ,  Can Zhu ,  Ruzhang Li ,  Guangbing Chen ,  Yuxin Wang ,  Xueliang Xu

IPC分类号： H03M1/12 ,  G11C27/02 ,  H03K17/687

CPC分类号： H03M1/1245 ,  G11C27/02 ,  H03K17/6871

摘要： A follow-hold switch circuit comprising: a follower; a sampling sub-circuit for voltage sampling; a bootstrap-control sub-circuit, which provides a bootstrap voltage to the sampling sub-circuit when the circuit is in a following state; a sampling-switch-control sub-circuit, which provides a common-mode voltage to a bootstrap capacitor in the bootstrap-control sub-circuit when the circuit is in a holding state; the follower is connected to an output of the sampling sub-circuit; the sampling sub-circuit is connected to the bootstrap-control sub-circuit and the sampling-switch-control sub-circuit respectively through a sampling switch; the present disclosure can effectively improve the linearity of sampling switches.

公开(公告)号：US11728820B2

公开(公告)日：2023-08-15

申请号：US17279101

申请日：2020-01-07

申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION ,  Chongqing GigaChip Technology Co., Ltd.

发明人： Daiguo Xu ,  Hequan Jiang ,  Xueliang Xu ,  Jian'an Wang ,  Guangbing Chen ,  Dongbing Fu ,  Yuxin Wang ,  Xiaoquan Yu ,  Shiliu Xu ,  Tao Liu

IPC分类号： H03M1/44 ,  H03M1/12 ,  H03K3/0233 ,  H03K19/017 ,  H03K19/17736

CPC分类号： H03M1/44 ,  H03K3/0233 ,  H03K19/01728 ,  H03K19/1774 ,  H03M1/125

摘要： The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.

公开(公告)号：US11936378B2

公开(公告)日：2024-03-19

申请号：US17925323

申请日：2021-01-06

申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION ,  Chongqing GigaChip Technology Co., Ltd.

发明人： Ting Li ,  Gangyi Hu ,  Ruzhang Li ,  Yong Zhang ,  Yabo Ni ,  Dongbing Fu ,  Jian'an Wang ,  Guangbing Chen

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521

摘要： An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.

公开(公告)号：US11476803B2

公开(公告)日：2022-10-18

申请号：US17616642

申请日：2020-01-07

申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION ,  CHONGQING GIGACHIP TECHNOLOGY CO. LTD.

发明人： Rongbin Hu ,  Ziqiang Yi ,  Gang Zhou ,  Dong Tang ,  Ning Tang ,  Daiguo Xu ,  Jianan Wang ,  Guangbing Chen ,  Dongbing Fu

IPC分类号： H03B5/24 ,  H03K4/56 ,  H03K3/012

摘要： The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents, and when the oscillating circuit is used to provide clock signals for the sensor, it can be integrated with a sensor signal processing circuit to realize the miniaturization and integration of the sensor system.

公开(公告)号：US11353505B2

公开(公告)日：2022-06-07

申请号：US17602993

申请日：2020-01-07

申请人： NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION ,  CHONGQING GIGACHIP TECHNOLOGY CO. LTD.

发明人： Mingyuan Xu ,  Liang Li ,  Jun Liu ,  Xiaofeng Shen ,  Jianan Wang ,  Dongbing Fu ,  Guangbing Chen ,  Xingfa Huang ,  Xi Chen

IPC分类号： G01R31/317 ,  H03K19/0948

摘要： The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK−) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK−) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.

公开(公告)号：US11664794B2

公开(公告)日：2023-05-30

申请号：US17609415

申请日：2020-01-07

申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION ,  Chongqing GigaChip Technology Co., Ltd.

发明人： Ting Li ,  Zhengbo Huang ,  Yong Zhang ,  Yabo Ni ,  Jian'an Wang ,  Guangbing Chen ,  Dongbing Fu ,  Zicheng Xu

IPC分类号： H03K5/24 ,  H03K3/037

CPC分类号： H03K5/2472 ,  H03K3/037

摘要： The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.

公开(公告)号：US11362666B2

公开(公告)日：2022-06-14

申请号：US17264298

申请日：2018-12-13

申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION

发明人： Tao Liu ,  Jian'an Wang ,  Yuxin Wang ,  Guangbing Chen ,  Dongbing Fu ,  Ruzhang Li ,  Shengdong Hu ,  Zhengping Zhang ,  Jun Luo ,  Daiguo Xu ,  Minming Deng ,  Yan Wang

IPC分类号： H03K23/00 ,  H03K23/44 ,  H03K3/356 ,  H03K5/15 ,  H03K23/42 ,  H03K23/50 ,  H03K23/52 ,  H03K23/66

摘要： The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

公开(公告)号：US10291245B2

公开(公告)日：2019-05-14

申请号：US15742835

申请日：2015-08-20

申请人： NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION

发明人： Jie Pu ,  Gangyi Hu ,  Xiaofeng Shen ,  Xueliang Xu ,  Dongbing Fu ,  Ruitao Zhang ,  Youhua Wang ,  Yuxin Wang ,  Guangbing Chen ,  Ruzhang Li

IPC分类号： H03M1/06 ,  H03M1/10

摘要： The present invention provides a device and method for correcting error estimation of an analog-to-digital converter. The method comprises: according to a preset initial value of a correction parameter, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to the initial value of a correction parameter, correcting a gain error between channels, generating a general correction signal, buffering the general correction signal and triggering a counting cell to start counting, and meanwhile calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting up to a preset value, setting enable ends of a low-pass filter accumulating cell and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching the error estimation result, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching the updated clock correction parameter and gain correction parameter, and resetting to carry out cyclic estimation correction. According to the present invention, in the case where a few effective sample points are used, the estimation accuracy is improved and the convergence rate of the estimation correction is increased.

公开(公告)号：US20180041221A1

公开(公告)日：2018-02-08

申请号：US15555071

申请日：2015-04-09

申请人： No. 24 Research Institute of China Electronics Technology Group Corporation

发明人： Daiguo Xu ,  Shiliu Xu ,  Gangyi Hu ,  Guangbing Chen ,  Lu Liu

IPC分类号： H03M1/44 ,  H03M1/12 ,  H03M1/06

CPC分类号： H03M1/442 ,  H03M1/068 ,  H03M1/069 ,  H03M1/1245 ,  H03M1/468

摘要： An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.