-
公开(公告)号：US20220224320A1
公开(公告)日：2022-07-14
申请号：US17609415
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , Chongqing GigaChip Technology Co., Ltd.
发明人： Ting LI , Zhengbo HUANG , Yong ZHANG , Yabo NI , Jian'an WANG , Guangbing CHEN , Dongbing FU , Zicheng XU
摘要： The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.
-
2.发明申请公开(公告)号：US20220224350A1
公开(公告)日：2022-07-14
申请号：US17614336
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , Chongqing GigaChip Technology Co., Ltd.
发明人： Tao LIU , Jian'an WANG , Yuxin WANG , Shengdong HU , Zhou YU , Minming DENG , Daiguo XU , Lu LIU , Dongbing FU , Jun LUO , Xu WANG , Yan WANG , Zicheng XU
摘要： A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2n clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.
-
公开(公告)号：US20210281269A1
公开(公告)日：2021-09-09
申请号：US17258165
申请日：2018-12-13
发明人： Ting LI , Gangyi HU , Ruzhang LI , Yong ZHANG , Zhengbo HUANG , Yabo NI , Xingfa HUANG , Jian'an WANG , Guangbing CHEN , Dongbing FU , Jun YUAN , Zicheng XU
IPC分类号： H03M1/06 , H03K5/02 , H03K17/687
摘要： The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current.
-
-
搜索结果
3 条记录 (耗时 0.015 秒)
