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公开(公告)号：US20220224320A1
公开(公告)日：2022-07-14
申请号：US17609415
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , Chongqing GigaChip Technology Co., Ltd.
发明人： Ting LI , Zhengbo HUANG , Yong ZHANG , Yabo NI , Jian'an WANG , Guangbing CHEN , Dongbing FU , Zicheng XU
摘要： The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.
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公开(公告)号：US20230216502A1
公开(公告)日：2023-07-06
申请号：US17925323
申请日：2021-01-06
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , Chongqing GigaChip Technology Co., Ltd.
发明人： Ting LI , Gangyi HU , Ruzhang LI , Yong ZHANG , Yabo NI , Dongbing FU , Jian'an WANG , Guangbing CHEN
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521
摘要： An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.
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3.发明申请公开(公告)号：US20210203344A1
公开(公告)日：2021-07-01
申请号：US17057702
申请日：2019-05-13
发明人： Ting LI , Zhengbo HUANG , Yong ZHANG , Yabo NI , Jian'an WANG , Dongbing FU
IPC分类号： H03M1/12 , G01R19/165 , H03M1/54
摘要： The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.
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公开(公告)号：US20210203277A1
公开(公告)日：2021-07-01
申请号：US17057698
申请日：2019-05-13
发明人： Ting LI , Zhengbo HUANG , Yong ZHANG , Yabo NI , Jian'an WANG , Dongbing FU
摘要： A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.
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公开(公告)号：US20210184689A1
公开(公告)日：2021-06-17
申请号：US17257315
申请日：2018-12-13
发明人： Jie PU , Gangyi HU , Dongbing FU , Zhengping ZHANG , Liang LI , Ting LI , Daiguo XU , Mingyuan XU , Xiaofeng SHEN , Xianjie WAN , Youhua WANG
摘要： The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.
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公开(公告)号：US20210135678A1
公开(公告)日：2021-05-06
申请号：US17257011
申请日：2018-07-25
发明人： Jie PU , Gangyi HU , Jian'an WANG , Guangbing CHEN , Liang LI , Ting LI , Daiguo XU , Xingfa HUANG , Xi CHEN , Tiehu LI , Youhua WANG
IPC分类号： H03M1/06
摘要： The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.
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7.发明申请公开(公告)号：US20210126646A1
公开(公告)日：2021-04-29
申请号：US16497806
申请日：2017-09-11
发明人： Zhengbo HUANG , Ting LI , Yong ZHANG , Ruzhang LI , Guangbing CHEN , Yabo NI
IPC分类号： H03M1/46
摘要： The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result. By using the pre-comparison and charge redistribution technologies, the number of comparators of different stages of pipelined sub ADC is reduced and the low power consumption design is achieved, signal sample-and-hold and residual signal amplification establishing are simultaneously carried out, thus improving the conversion rate.
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公开(公告)号：US20220321136A1
公开(公告)日：2022-10-06
申请号：US17623613
申请日：2019-07-26
发明人： Ting LI , Gangyi HU , Ruzhang LI , Yong ZHANG , Dongbing FU , Zhengbo HUANG , Yabo NI , Jian'an WANG , Guangbing CHEN
IPC分类号： H03M1/10
摘要： A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.
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公开(公告)号：US20210281269A1
公开(公告)日：2021-09-09
申请号：US17258165
申请日：2018-12-13
发明人： Ting LI , Gangyi HU , Ruzhang LI , Yong ZHANG , Zhengbo HUANG , Yabo NI , Xingfa HUANG , Jian'an WANG , Guangbing CHEN , Dongbing FU , Jun YUAN , Zicheng XU
IPC分类号： H03M1/06 , H03K5/02 , H03K17/687
摘要： The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current.
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公开(公告)号：US20210013896A1
公开(公告)日：2021-01-14
申请号：US16620879
申请日：2018-07-18
发明人： Yong ZHANG , Ting LI , Zhengbo HUANG , Yabo NI , Dongbing FU
IPC分类号： H03M1/10
摘要： The present disclosure relates to the field of semiconductor integrated circuits, and to a method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC). The method includes: calibrating a voltage coefficient; obtaining a sampled charged charge according to a capacitance model with the voltage coefficient; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient; and then calibrating the second-order capacitor voltage coefficient in a digital domain. In the present disclosure, a capacitor voltage coefficient can be extracted based on INL and the capacitor voltage coefficient is calibrated at a digital backend without adding an analog calibration circuit, thereby improving conversion accuracy of the ADC.
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