公开(公告)号：US20230188468A1

公开(公告)日：2023-06-15

申请号：US17548456

申请日：2021-12-10

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： Brian Alleyne ,  Mimi Dannhardt ,  Evan Gewirtz ,  Hengwei Hsu ,  Alexander Shechter ,  Sakthi Subramanian ,  Mohamed Abdul Malick Mohamed Usman

IPC: H04L47/125 ,  H04L47/28 ,  H04L49/103

CPC classification number: H04L47/125 ,  H04L47/28 ,  H04L49/103

Abstract: Systems and methods for flowlet switching using memory instructions. One embodiment is a method of distributing packets over multiple paths. The method includes determining an elapsed time between a packet and a previous packet. The method further includes, in response to determining that the elapsed time is less than an inter-packet gap threshold: retaining a previously selected path value indicated in the flow record, and providing the previously selected path value to the processing thread for transmitting the packet over a previously selected path associated with the previous packet. The method also further includes, in response to determining that the elapsed time is greater than the inter-packet gap threshold: updating the flow record by replacing the previously selected path value with the path value of the selected path of the memory instruction, and providing the path value to the processing thread for transmitting the packet over the selected path.

公开(公告)号：US20230188467A1

公开(公告)日：2023-06-15

申请号：US17548451

申请日：2021-12-10

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： Brian Alleyne ,  Matias Cavuoti ,  Li-Chuan Egan ,  Mimi Dannhardt ,  Krishnan Subramani ,  Mohamed Abdul Malick Mohamed Usman ,  Roxanna Ganji ,  Stephen Russell

IPC: H04L47/122 ,  H04L47/32 ,  H04L47/52 ,  H04L47/10

CPC classification number: H04L47/122 ,  H04L47/29 ,  H04L47/326 ,  H04L47/521

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, and external memory configured to provide a backing store to the on-chip memory. The network processor also includes a processor configured, in response to determining that the source device is unresponsive to a congestion notification, to reduce a size of one or more queues to prevent packets transferring from the on-chip memory to the external memory.

公开(公告)号：US11985067B2

公开(公告)日：2024-05-14

申请号：US17548456

申请日：2021-12-10

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： Brian Alleyne ,  Mimi Dannhardt ,  Evan Gewirtz ,  Hengwei Hsu ,  Alexander Shechter ,  Sakthi Subramanian ,  Mohamed Abdul Malick Mohamed Usman

IPC: H04L47/125 ,  H04L47/28 ,  H04L49/103

CPC classification number: H04L47/125 ,  H04L47/28 ,  H04L49/103

Abstract: Systems and methods for flowlet switching using memory instructions. One embodiment is a method of distributing packets over multiple paths. The method includes determining an elapsed time between a packet and a previous packet. The method further includes, in response to determining that the elapsed time is less than an inter-packet gap threshold: retaining a previously selected path value indicated in the flow record, and providing the previously selected path value to the processing thread for transmitting the packet over a previously selected path associated with the previous packet. The method also further includes, in response to determining that the elapsed time is greater than the inter-packet gap threshold: updating the flow record by replacing the previously selected path value with the path value of the selected path of the memory instruction, and providing the path value to the processing thread for transmitting the packet over the selected path.

公开(公告)号：US20230188447A1

公开(公告)日：2023-06-15

申请号：US17548438

申请日：2021-12-10

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： Brian Alleyne ,  Matias Cavuoti ,  Li-Chuan Egan ,  Mimi Dannhardt ,  Krishnan Subramani ,  Mohamed Abdul Malick Mohamed Usman ,  Roxanna Ganji ,  Stephen Russell

IPC: H04L43/0882 ,  H04L43/0811 ,  H04L43/0817 ,  H04L43/0894 ,  H04L47/122

CPC classification number: H04L43/0882 ,  H04L43/0811 ,  H04L43/0817 ,  H04L43/0894 ,  H04L47/122

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, an external memory interface configured to couple the on-chip memory with an external memory providing a backing store to the on-chip memory, and bandwidth monitor configured to measure a bandwidth utilization of the external memory. The network processor also includes a processor configured to apply the bandwidth utilization of the external memory to a congestion notification profile, to generate one or more congestion notifications based on the bandwidth utilization applied to the congestion notification profile, and to send the one or more congestion notifications to the source device to request decreasing packet rate for decreasing the bandwidth utilization of the external memory.

公开(公告)号：US12126513B2

公开(公告)日：2024-10-22

申请号：US17548438

申请日：2021-12-10

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： Brian Alleyne ,  Matias Cavuoti ,  Li-Chuan Egan ,  Mimi Dannhardt ,  Krishnan Subramani ,  Mohamed Abdul Malick Mohamed Usman ,  Roxanna Ganji ,  Stephen Russell

IPC: H04L43/0882 ,  H04L43/0811 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L47/12 ,  H04L47/122

CPC classification number: H04L43/0882 ,  H04L43/0811 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L47/12 ,  H04L47/122

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, an external memory interface configured to couple the on-chip memory with an external memory providing a backing store to the on-chip memory, and bandwidth monitor configured to measure a bandwidth utilization of the external memory. The network processor also includes a processor configured to apply the bandwidth utilization of the external memory to a congestion notification profile, to generate one or more congestion notifications based on the bandwidth utilization applied to the congestion notification profile, and to send the one or more congestion notifications to the source device to request decreasing packet rate for decreasing the bandwidth utilization of the external memory.

公开(公告)号：US11895029B2

公开(公告)日：2024-02-06

申请号：US17548451

申请日：2021-12-10

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： Brian Alleyne ,  Matias Cavuoti ,  Li-Chuan Egan ,  Mimi Dannhardt ,  Krishnan Subramani ,  Mohamed Abdul Malick Mohamed Usman ,  Roxanna Ganji ,  Stephen Russell

IPC: H04L47/00 ,  H04L47/122 ,  H04L47/10 ,  H04L47/52 ,  H04L47/32

CPC classification number: H04L47/122 ,  H04L47/29 ,  H04L47/326 ,  H04L47/521

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, and external memory configured to provide a backing store to the on-chip memory. The network processor also includes a processor configured, in response to determining that the source device is unresponsive to a congestion notification, to reduce a size of one or more queues to prevent packets transferring from the on-chip memory to the external memory.