公开(公告)号：US09425110B1

公开(公告)日：2016-08-23

申请号：US14837718

申请日：2015-08-27

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Jose G. Padilla ,  Philip W. Hon ,  Shih-En Shih ,  Roger S. Tsai ,  Xianglin Zeng

IPC: H01L21/66 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/66

CPC classification number: H01L22/22 ,  H01L22/14 ,  H01L22/32 ,  H01L23/66 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6616 ,  H01L2223/6683 ,  H01L2225/06555 ,  H01L2225/06596

Abstract: A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.

Abstract translation: 三维晶片级封装（WLP）集成电路，其包括一对相对的电路单元，其在单独的晶片上制造，所述相对电路单元已经被结合在一起以提供垂直电路冗余。 每个单独的晶片之间的集成电路在晶片被接合在一起之前进行性能测试，以便将表现良好的电路指定为有源电路单元，并且作为不活动电路单元的执行不良电路。 用于特定对集成电路的非活动电路单元用短路金属层进行金属化，以使其不可操作。 WLP集成电路在空间不相关的晶片上实现了屈服增强电路冗余方案，避免了浪费有价值的晶圆xy平面区域，由于更多的晶片面积可用于每个晶片上的不同电路，因此可以节省成本，而不是牺牲传统方面 - 电路的冗余副本。