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    Micro hermetic sensor
    5.
    发明授权
    Micro hermetic sensor 有权

    公开(公告)号：US10132712B1

    公开(公告)日：2018-11-20

    申请号：US15265135

    申请日：2016-09-14

    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

    Inventor： Chunbo Zhang ,  Phuong Nguyen ,  Xianglin Zeng ,  Maria L. Tenorio

    IPC: G01K17/00 ,  G01N25/72 ,  G01M3/00 ,  H01L21/67 ,  H01L21/66 ,  H01L23/31

    Abstract: A sensor assembly for determining whether a hermetically sealed cavity between opposing substrate wafers in a wafer level packaged (WLP) chip is leaking. The sensor assembly includes a thermal insulating layer provided within the cavity, and a heater and temperature sensor deposited on the insulation layer. The thermal insulating layer is made of a suitable dielectric that is compatible with WLP and MMIC fabrication processes and can be, for example, benzocyclobutene (BCB) or polyimide. The sensor is responsive to a current that heats the thermal insulation layer so that heat dissipated by the thermal insulation layer is drawn away by gas between the layer and the substrate that determines the temperature of the sensor, which is detected.

    Yield enhancing vertical redundancy method for 3D wafer level packaged (WLP) integrated circuit systems
    8.
    发明授权
    Yield enhancing vertical redundancy method for 3D wafer level packaged (WLP) integrated circuit systems 有权
    用于3D晶片级封装（WLP）集成电路系统的增益垂直冗余方法

    公开(公告)号：US09425110B1

    公开(公告)日：2016-08-23

    申请号：US14837718

    申请日：2015-08-27

    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

    Inventor： Jose G. Padilla ,  Philip W. Hon ,  Shih-En Shih ,  Roger S. Tsai ,  Xianglin Zeng

    IPC: H01L21/66 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/66

    CPC classification number: H01L22/22 ,  H01L22/14 ,  H01L22/32 ,  H01L23/66 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6616 ,  H01L2223/6683 ,  H01L2225/06555 ,  H01L2225/06596

    Abstract: A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.

    Abstract translation: 三维晶片级封装（WLP）集成电路，其包括一对相对的电路单元，其在单独的晶片上制造，所述相对电路单元已经被结合在一起以提供垂直电路冗余。 每个单独的晶片之间的集成电路在晶片被接合在一起之前进行性能测试，以便将表现良好的电路指定为有源电路单元，并且作为不活动电路单元的执行不良电路。 用于特定对集成电路的非活动电路单元用短路金属层进行金属化，以使其不可操作。 WLP集成电路在空间不相关的晶片上实现了屈服增强电路冗余方案，避免了浪费有价值的晶圆xy平面区域，由于更多的晶片面积可用于每个晶片上的不同电路，因此可以节省成本，而不是牺牲传统方面 - 电路的冗余副本。

    Integrated micro-plasma limiter
    9.
    发明授权
    Integrated micro-plasma limiter 有权
    集成微型等离子体限制器

    公开(公告)号：US09054500B2

    公开(公告)日：2015-06-09

    申请号：US13865921

    申请日：2013-04-18

    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

    Inventor： Patty Chang-Chien ,  Kelly Jill Hennig ,  Xianglin Zeng ,  Jeffrey M. Yang

    IPC: H01T4/16 ,  H03G11/00 ,  H01P1/14 ,  H01L23/60

    CPC classification number: H01T4/16 ,  H01L23/60 ,  H01L2924/0002 ,  H01P1/14 ,  H03G11/002 ,  H03G11/004 ,  H01L2924/00

    Abstract: A plasma power limiter fabricated using wafer-level fabrication techniques with other circuit elements. The plasma limiter includes a signal substrate and a trigger substrate defining a hermetically sealed cavity therebetween in which is encapsulated an ionizable gas. The signal substrate includes a signal line within the cavity and the trigger substrate includes at least one trigger probe extending from the trigger substrate towards the transmission line. If a signal propagating on the transmission line exceeds a power threshold, the gas within the cavity is ionized creating a conduction path between the transmission line and the trigger probe that draws off the high power current.

    Abstract translation: 使用晶圆级制造技术与其他电路元件制造的等离子体功率限制器。 等离子体限制器包括信号基板和触发基板，其在其间限定密封腔，其中封装有可电离气体。 信号衬底包括腔内的信号线，并且触发衬底包括从触发衬底朝向传输线延伸的至少一个触发探针。 如果在传输线上传播的信号超过功率阈值，则空腔内的气体被电离，在传输线和触发探头之间产生一个导通路径，从而消除高功率电流。

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