公开(公告)号：US20240355701A1

公开(公告)日：2024-10-24

申请号：US18630530

申请日：2024-04-09

Applicant: AARON ASHLEY HATHAWAY ,  GREGORY R. BOYD ,  JOHN X. PRZYBYSZ

Inventor： AARON ASHLEY HATHAWAY ,  GREGORY R. BOYD ,  JOHN X. PRZYBYSZ

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66

CPC classification number: H01L23/367 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53285 ,  H01L23/66 ,  H01L2223/6605 ,  H01L2223/6683

Abstract: An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

公开(公告)号：US12125806B2

公开(公告)日：2024-10-22

申请号：US18219422

申请日：2023-07-07

Applicant: Wolfspeed, Inc.

Inventor： Arthur Pun ,  Basim Noori

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/047 ,  H01L23/29 ,  H01L23/495 ,  H01L23/66

CPC classification number: H01L23/564 ,  H01L21/4817 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/047 ,  H01L23/293 ,  H01L23/296 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/66 ,  H01L2223/6683

Abstract: A method of packaging an RF transistor device includes attaching one or more electronic devices to a carrier substrate, applying an encapsulant over at least one of the one or more electronic devices, and providing a protective structure on the carrier substrate over the one or more electronic devices. A packaged RF transistor device includes a carrier substrate, one or more electronic devices attached to the carrier substrate, an encapsulant material over at least one of the one or more electronic devices and extending onto the carrier substrate, and a protective structure on the carrier substrate over the one or more electronic devices and the encapsulant material.

公开(公告)号：US12080708B2

公开(公告)日：2024-09-03

申请号：US18306342

申请日：2023-04-25

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： James Joseph Brogle ,  Joseph Gerard Bukowski ,  Margaret Mary Barter ,  Timothy Edward Boles

IPC: H01L27/06 ,  H01L21/225 ,  H01L21/265 ,  H01L23/66 ,  H01L27/08 ,  H01L29/868 ,  H01L21/822 ,  H01L29/66

CPC classification number: H01L27/0676 ,  H01L21/2253 ,  H01L21/2254 ,  H01L21/26513 ,  H01L23/66 ,  H01L27/0814 ,  H01L29/868 ,  H01L21/822 ,  H01L29/6609 ,  H01L2223/6627 ,  H01L2223/6666 ,  H01L2223/6683

Abstract: A number of diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a diode limiter includes a first diode having a first doped region formed to a first depth into an intrinsic layer of a semiconductor structure, a second diode having a second doped region formed to a second depth into the intrinsic layer of the semiconductor structure, and at least one passive component. The first diode includes a first effective intrinsic region of a first thickness, the second diode includes a second effective intrinsic region of a second thickness. The first thickness is greater than the second thickness. The passive component is over the intrinsic layer and electrically coupled as part of the diode limiter.

公开(公告)号：US12027437B2

公开(公告)日：2024-07-02

申请号：US17222238

申请日：2021-04-05

Applicant: Aaron Ashley Hathaway ,  Gregory R. Boyd ,  John X. Przybysz

Inventor： Aaron Ashley Hathaway ,  Gregory R. Boyd ,  John X. Przybysz

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66

CPC classification number: H01L23/367 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53285 ,  H01L23/66 ,  H01L2223/6605 ,  H01L2223/6683

Abstract: An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

公开(公告)号：US11948838B2

公开(公告)日：2024-04-02

申请号：US18168753

申请日：2023-02-14

Applicant: Qorvo US, Inc.

Inventor： Deep C. Dumka

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/3065 ,  H01L23/48 ,  H01L23/66 ,  H01L25/065 ,  H01L29/06

CPC classification number: H01L21/76898 ,  H01L21/304 ,  H01L21/3065 ,  H01L23/481 ,  H01L23/66 ,  H01L25/0657 ,  H01L29/0649 ,  H01L2223/6683

Abstract: The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

公开(公告)号：US11824249B2

公开(公告)日：2023-11-21

申请号：US18058383

申请日：2022-11-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jun-De Jin

IPC: H01P3/00 ,  H01L23/66 ,  H01P11/00

CPC classification number: H01P3/003 ,  H01L23/66 ,  H01P11/003 ,  H01L2223/6627 ,  H01L2223/6683

Abstract: A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.

公开(公告)号：US20230335524A1

公开(公告)日：2023-10-19

申请号：US18334280

申请日：2023-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： Angelo SCUDERI ,  Nicola MARINELLI

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L24/17 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/14133 ,  H01L2224/16225 ,  H01L2224/17133 ,  H01L2224/48105 ,  H01L2224/48225 ,  H01L2224/73257 ,  H01L2924/1423

Abstract: An electronic device has a plurality of integrated circuits fixed to a support between transmitting and receiving antennas. An integrated circuit generates a synchronization signal supplied to the other integrated circuits. Each integrated circuit is formed in a die integrating electronic components and overlaid by a connection region according to the Flip-Chip Ball-Grid-array or embedded Wafer Level BGA. A plurality of solder balls for each integrated circuit is electrically coupled to the electronic components and bonded between the respective integrated circuit and the support. The solder balls are arranged in an array, aligned along a plurality of lines parallel to a direction, wherein the plurality of lines comprises an empty line along which no solder balls are present. A conductive synchronization path is formed on the support and extends along the empty line of at least one integrated circuit, between the solder balls of the latter.

公开(公告)号：US11791389B2

公开(公告)日：2023-10-17

申请号：US17144346

申请日：2021-01-08

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Jia Guo ,  Jeremy Fisher ,  Scott Sheppard

IPC: H01L29/417 ,  H01L23/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H03F3/195 ,  H03F3/213

CPC classification number: H01L29/41775 ,  H01L23/66 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H03F3/195 ,  H03F3/213 ,  H01L2223/6644 ,  H01L2223/6683 ,  H03F2200/451

Abstract: A gallium nitride-based RF transistor amplifier comprises a semiconductor layer structure comprising a barrier layer on a channel layer, first and second source/drain regions in the semiconductor layer structure, first and second source/drain contacts on the respective first and second source/drain regions, and a longitudinally-extending gate finger that is between the first and second source/drain contacts. The first and second source/drain contacts each has an inner sidewall that faces the gate finger and an opposed outer sidewall. The first source/drain region extends a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure, and extends a second, smaller distance from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region.

公开(公告)号：US11737154B2

公开(公告)日：2023-08-22

申请号：US17462855

申请日：2021-08-31

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing

IPC: H01L23/66 ,  H04W76/10 ,  H01L25/065 ,  H01L25/16 ,  H01Q1/22 ,  H04B1/48 ,  H01L23/00 ,  H04Q1/02 ,  H05K7/14 ,  H01Q3/30 ,  H04B1/38

CPC classification number: H04W76/10 ,  H01L23/66 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01Q1/2266 ,  H01Q1/2283 ,  H04B1/48 ,  H04Q1/15 ,  H05K7/1487 ,  H01L24/16 ,  H01L24/73 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2223/6688 ,  H01L2224/16221 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/1033 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1421 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/19105 ,  H01Q3/30 ,  H04B1/38

Abstract: A patch on interposer (PoINT) package is described with a wireless communications interface. Some examples include an interposer, a main patch attached to the interposer, a main integrated circuit die attached to the patch, a second patch attached to the interposer, and a millimeter wave radio die attached to the second patch and coupled to the main integrated circuit die through the interposer to communicate data between the main die and an external component.

公开(公告)号：US11699629B2

公开(公告)日：2023-07-11

申请号：US17213974

申请日：2021-03-26

Applicant: Qorvo US, Inc.

Inventor： Anthony Chiu ,  Bror Peterson ,  Andrew Ketterson

IPC: H01L23/367 ,  H01L23/373 ,  H01L25/18 ,  H01L23/48 ,  H01L23/66 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L23/367 ,  H01L23/3736 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/66 ,  H01L24/29 ,  H01L24/32 ,  H01L25/18 ,  H01L28/90 ,  H01L2223/6683 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32265

Abstract: The disclosure is directed to an integrated circuit (IC) die stacked with a backer die, including capacitors and thermal vias. The backer die includes a substrate material to contain and electrically insulate one or more capacitors at a back of the IC die. The backer die further includes a thermal material that is more thermally conductive than the substrate material for thermal spreading and increased heat dissipation. In particular, the backer die electrically couples capacitors to the IC die in a stacked configuration while also spreading and dissipating heat from the IC die. Such a configuration reduces an overall footprint of the electronic device, resulting in decreased integrated circuits (IC) packages and module sizes. In other words, instead of placing the capacitors next to the IC die, the capacitors are stacked on top of the IC die, thereby reducing an overall surface area of the package.