公开(公告)号：US09577083B1

公开(公告)日：2017-02-21

申请号：US15072261

申请日：2016-03-16

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Yeong-Chang Chou ,  Richard Lai ,  Quin W. Kan ,  Keang H. Kho ,  Hsu-Hwei Chen ,  Matthew R. Parlee

IPC: H01L29/20 ,  H01L23/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/47 ,  H01L29/423 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/3171 ,  H01L23/291 ,  H01L23/66 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7785 ,  H01L2223/6683

Abstract: A field effect transistor (FET) device including a substrate and a plurality of semiconductor layers provided on the substrate, where a top semiconductor layer is a heavily doped cap layer and another one of the semiconductor layers directly below the cap layer is a Schottky barrier layer, and where a gate recess is formed through the cap layer and into the Schottky barrier layer. The FET device also includes a gate terminal having a titanium layer, an inhibitor layer provided on the titanium layer and a gold layer provided on the inhibitor layer, where the gate terminal is formed in the recess so that the titanium layer is in contact with the Schottky barrier layer, and where the inhibitor layer is effective for preventing hydrogen gas from being dissociated into hydrogen atoms so as to reduce or prevent hydrogen poisoning of the FET device.

Abstract translation: 包括衬底和设置在衬底上的多个半导体层的场效应晶体管（FET）器件，其中顶部半导体层是重掺杂的帽层，并且覆盖层正下方的另一个半导体层是肖特基势垒层 并且其中通过盖层形成栅极凹槽并进入肖特基势垒层。 FET器件还包括具有钛层的栅极端子，设置在钛层上的抑制层和设置在抑制层上的金层，其中栅极端子形成在凹槽中，使钛层与 肖特基势垒层，并且其中抑制剂层对于防止氢气解离成氢原子是有效的，以便减少或防止FET器件的氢中毒。

公开(公告)号：US09882000B2

公开(公告)日：2018-01-30

申请号：US15163375

申请日：2016-05-24

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Stephen J. Sarkozy ,  Yaochung Chen ,  Richard Lai

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/22 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/0657 ,  H01L29/22 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/66522 ,  H01L29/7783

Abstract: A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer deposited on the semiconductor layers. The FET also includes a plurality of castellation structures formed on the heavily doped gate layer and being spaced apart from each other, where each castellation structure includes at least one channel layer. A gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer. A voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.