公开(公告)号：US12019498B2

公开(公告)日：2024-06-25

申请号：US16175232

申请日：2018-10-30

申请人： NVIDIA Corporation

发明人： Thomas E. Dewey ,  Narayan Kulshrestha ,  Ramachandiran V ,  Sachin Idgunji ,  Lordson Yue

IPC分类号： G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/42 ,  G06F15/78 ,  G06T1/20 ,  G06T15/00

CPC分类号： G06F1/3287 ,  G06F1/3243 ,  G06F1/3278 ,  G06F1/3296 ,  G06F13/4221 ,  G06F15/7807 ,  G06T1/20 ,  G06T15/005 ,  G06F2213/0026

摘要： An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.

公开(公告)号：US20130249897A1

公开(公告)日：2013-09-26

申请号：US13727965

申请日：2012-12-27

申请人： NVIDIA CORPORATION

发明人： Jonathan Dunaisky ,  David Kirk McAllister ,  Steven E. Molnar ,  Narayan Kulshrestha ,  Rui Bastos ,  Joseph Detmer ,  William Craig McKnight

IPC分类号： G06T5/00

CPC分类号： G06T5/002 ,  G06T9/00 ,  G09G5/363 ,  G09G5/39 ,  G09G2340/02 ,  G09G2340/10 ,  G09G2360/06 ,  G09G2360/121 ,  G09G2360/122 ,  H04N19/426

摘要： A method for compressing framebuffer data is presented. The method includes determining a reduction ratio for framebuffer data in a tile including multiple samples. The reduction ratio determined is independent of the sampling mode, where the sampling mode is the number of samples within each pixel in the tile. The method further includes comparing a first portion of the framebuffer data for each of the multiple samples to determine an equality comparison result and also comparing a second portion of the framebuffer data for each one of the multiple samples to compute per-channel differences for each one of the multiple samples and testing the per-channel differences against a threshold value to determine a threshold comparison result. Finally, the method comprises compressing the framebuffer data for the tile based on the reduction ratio, the equality comparison result and the threshold comparison result to produce output framebuffer data for the tile.

摘要翻译： 提出了一种压缩帧缓冲器数据的方法。 该方法包括确定包括多个样本的瓦片中的帧缓冲器数据的缩小率。 确定的减小比率与采样模式无关，其中采样模式是瓦片中每个像素内的采样数。 该方法还包括比较多个样本中的每一个的帧缓冲器数据的第一部分以确定相等比较结果，并且还比较多个样本中的每一个样本的帧缓冲器数据的第二部分，以计算每个样本的每个信道差异 并且测试每个通道的差异与阈值以确定阈值比较结果。 最后，该方法包括基于缩小比率，等式比较结果和阈值比较结果压缩瓦片的帧缓冲器数据，以产生瓦片的输出帧缓冲器数据。

公开(公告)号：US12032840B2

公开(公告)日：2024-07-09

申请号：US17678784

申请日：2022-02-23

申请人： NVIDIA CORPORATION

发明人： Anand Shanmugam Sundararajan ,  Narayan Kulshrestha ,  Ka Yun Lee ,  Brian Smith ,  Madhukiran V. Swarna ,  Ramachandiran V ,  Kevin Wilder

IPC分类号： G06F3/06

CPC分类号： G06F3/0634 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

摘要： Various embodiments include a computer memory system that dynamically adjusts a memory device performance feature, such as dynamic assist control, dynamic turbo mode, and/or the like, to improve the performance of memory devices in the memory system. The memory system enables or disables the memory device performance feature based on the operating voltage relative to a threshold voltage. If the operating voltage crosses the threshold voltage in one direction, then the memory device system enables the memory device performance feature. If the operating voltage crosses the threshold voltage in another direction, then the memory system disables the memory device performance feature. Various techniques enable the memory device performance feature to be employed even with complex integrated circuits that may include tens of thousands of devices that employ the memory device performance feature.

公开(公告)号：US11106261B2

公开(公告)日：2021-08-31

申请号：US16179620

申请日：2018-11-02

申请人： NVIDIA Corporation

发明人： Aniket Naik ,  Siddharth Bhargav ,  Bardia Zandian ,  Narayan Kulshrestha ,  Amit Pabalkar ,  Arvind Gopalakrishnan ,  Justin Tai ,  Sachin Satish Idgunji

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/3206 ,  G06F9/50 ,  G06F1/3296 ,  G06F1/28 ,  G06N20/00 ,  G06N5/04

摘要： Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.

公开(公告)号：US08624916B2

公开(公告)日：2014-01-07

申请号：US13854274

申请日：2013-04-01

申请人： NVIDIA Corporation

发明人： Narayan Kulshrestha ,  Adam Paul Dreyer ,  Chad D. Walker ,  Rui M. Bastos

IPC分类号： G06T1/00 ,  G06F13/00 ,  G09G5/36 ,  G06F12/00 ,  G06F15/00 ,  G06F9/00 ,  G06K9/60 ,  H04N1/46 ,  G03F3/08

CPC分类号： G06T1/20 ,  G06F9/3004 ,  G06F9/30087

摘要： One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.

摘要翻译： 本发明的一个实施例阐述了被配置为执行彩色光栅操作和原子事务两者的CROP。 在接收到原子事务时，CROP内的分发单元向L2缓存发送读取请求以检索目的地操作数。 分配单元还将源操作数和操作代码发送到等待时间缓冲器用于存储，直到从L2高速缓存检索目的地操作数。 处理流水线将操作码，源和目的地操作数和原子标志传送到混合单元进行处理。 混合单元基于操作代码在源操作数和目标操作数上执行原子事务处理，并将原子事务的结果返回到处理流水线以存储在内部缓存中。 处理流水线将原子事务的结果写入L2高速缓存以存储在与原子事务相关联的存储单元处。

公开(公告)号：US09530189B2

公开(公告)日：2016-12-27

申请号：US13727965

申请日：2012-12-27

申请人： NVIDIA Corporation

发明人： Jonathan Dunaisky ,  David Kirk McAllister ,  Steven E. Molnar ,  Narayan Kulshrestha ,  Rui Bastos ,  Joseph Detmer ,  William Craig McKnight

IPC分类号： G06T15/30 ,  G09G5/00 ,  G09G5/02 ,  G03F3/08 ,  G06K9/00 ,  G06K9/40 ,  G06K9/36 ,  G09G5/36 ,  G06T5/00 ,  G06T9/00 ,  H04N19/426 ,  G09G5/39

CPC分类号： G06T5/002 ,  G06T9/00 ,  G09G5/363 ,  G09G5/39 ,  G09G2340/02 ,  G09G2340/10 ,  G09G2360/06 ,  G09G2360/121 ,  G09G2360/122 ,  H04N19/426

摘要： A method for compressing framebuffer data is presented. The method includes determining a reduction ratio for framebuffer data in a tile including multiple samples. The reduction ratio determined is independent of the sampling mode, where the sampling mode is the number of samples within each pixel in the tile. The method further includes comparing a first portion of the framebuffer data for each of the multiple samples to determine an equality comparison result and also comparing a second portion of the framebuffer data for each one of the multiple samples to compute per-channel differences for each one of the multiple samples and testing the per-channel differences against a threshold value to determine a threshold comparison result. Finally, the method comprises compressing the framebuffer data for the tile based on the reduction ratio, the equality comparison result and the threshold comparison result to produce output framebuffer data for the tile.

摘要翻译： 提出了一种压缩帧缓冲器数据的方法。 该方法包括确定包括多个样本的瓦片中的帧缓冲器数据的缩小率。 确定的减小比率与采样模式无关，其中采样模式是瓦片中每个像素内的采样数。 该方法还包括比较多个样本中的每一个的帧缓冲器数据的第一部分以确定相等比较结果，并且还比较多个样本中的每一个样本的帧缓冲器数据的第二部分，以计算每个样本的每个信道差异 并且测试每个通道的差异与阈值以确定阈值比较结果。 最后，该方法包括基于缩小比率，等式比较结果和阈值比较结果压缩瓦片的帧缓冲器数据，以产生瓦片的输出帧缓冲器数据。