公开(公告)号：US20140125669A1

公开(公告)日：2014-05-08

申请号：US13671456

申请日：2012-11-07

Applicant: NVIDIA CORPORATION

Inventor： Emmett M. KILGARIFF ,  Morgan McGUIRE ,  Yury Y. URALSKY ,  Ziyad S. HAKURA

IPC: G06T15/80 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06T15/00 ,  G06T15/005 ,  G09G5/363

Abstract: Techniques are disclosed for processing graphics objects in a stage of a graphics processing pipeline. The techniques include receiving a graphics primitive associated with the graphics object, and determining a plurality of attributes corresponding to one or more vertices associated with the graphics primitive. The techniques further include determining values for one or more state parameters associated with a downstream stage of the graphics processing pipeline based on a visual effect associated with the graphics primitive. The techniques further include transmitting the state parameter values to the downstream stage of the graphics processing pipeline. One advantage of the disclosed techniques is that visual effects are flexibly and efficiently performed.

Abstract translation: 公开了用于在图形处理流水线的阶段处理图形对象的技术。 这些技术包括接收与图形对象相关联的图形基元，以及确定与图形基元相关联的一个或多个顶点对应的多个属性。 这些技术还包括基于与图形基元相关联的视觉效果来确定与图形处理流水线的下游级相关联的一个或多个状态参数的值。 所述技术还包括将状态参数值发送到图形处理流水线的下游阶段。 所公开的技术的一个优点是灵活和有效地执行视觉效果。

公开(公告)号：US20140118376A1

公开(公告)日：2014-05-01

申请号：US14046856

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Walter R. STEINER ,  Cynthia Ann Edgeworth ALLISON ,  Rouslan DIMITROV ,  Karim M. ABDALLA ,  Dale L. KIRKLAND ,  Emmett M. KILGARIFF

IPC: G09G5/00

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the first plurality of graphics primitives should be replayed from the buffer, and, in response, replaying the first plurality of graphics primitives against a first tile included in a first plurality of tiles. Replaying the first plurality of graphics primitives includes comparing each graphics primitive against the first tile to determine whether the graphics primitive intersects the first tile, determining that one or more graphics primitives intersects the first tile, and transmitting the one or more graphics primitives and one or more associated state bundles to a screen-space pipeline for processing.

Abstract translation: 本发明的一个实施例包括一种在基于瓦片的架构中处理图形基元的技术。 该技术包括在缓冲器中存储从世界空间管道接收的第一多个图形基元和第一多个状态束。 该技术还包括基于第一条件确定第一多个图形基元应该从缓冲器重放，并且作为响应，针对包括在第一多个瓦片中的第一瓦片重播第一多个图形基元。 重放第一多个图形基元包括比较每个图形原语与第一图块以确定图形基元是否与第一图块相交，确定一个或多个图形图元与第一图块相交，以及发送一个或多个图形图元，以及一个或多个图形基元 更多关联的状态束到屏幕空间管线进行处理。

公开(公告)号：US20140122812A1

公开(公告)日：2014-05-01

申请号：US14016847

申请日：2013-09-03

Applicant: NVIDIA Corporation

Inventor： Ziyad S. HAKURA ,  Emmett M. KILGARIFF

IPC: G06F12/08

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention sets forth a graphics subsystem. The graphics subsystem includes a first tiling unit associated with a first set of raster tiles and a crossbar unit. The crossbar unit is configured to transmit a first set of primitives to the first tiling unit and to transmit a first cache invalidate command to the first tiling unit. The first tiling unit is configured to determine that a second bounding box associated with primitives included in the first set of primitives overlaps a first cache tile and that the first bounding box overlaps the first cache tile. The first tiling unit is further configured to transmit the primitives and the first cache invalidate command to a first screen-space pipeline associated with the first tiling unit for processing. The screen-space pipeline processes the cache invalidate command to invalidate cache lines specified by the cache invalidate command.

Abstract translation: 本发明的一个实施例阐述了一个图形子系统。 图形子系统包括与第一组栅格瓦片和横杆单元相关联的第一平铺单元。 交叉开关单元被配置为将第一组图元发送到第一拼接单元并且向第一拼接单元发送第一高速缓存无效命令。 第一平铺单元被配置为确定与包括在第一组图元中的图元相关联的第二边界框与第一高速缓存块重叠，并且第一边界框与第一高速缓存块重叠。 第一平铺单元还被配置为将原语和第一高速缓存无效命令发送到与第一拼接单元相关联的第一屏幕空间管线用于处理。 屏幕空间管道处理缓存无效命令，使缓存无效命令指定的缓存行无效。

公开(公告)号：US20140152652A1

公开(公告)日：2014-06-05

申请号：US14082669

申请日：2013-11-18

Applicant: NVIDIA CORPORATION

Inventor： Steven E. MOLNAR ,  Emmett M. KILGARIFF ,  John S. RHOADES ,  Timothy John PURCELL ,  Sean J. TREICHLER ,  Ziyad S. HAKURA ,  Franklin C. CROW ,  James C. BOWMAN

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T2210/52

Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

Abstract translation: 本发明的一个实施例提出了一种用于在保持API原语排序的同时并行渲染图形基元的技术。 多个独立的几何单元在不同的图形基元上同时执行几何处理。 原始分配方案以每个时钟的多个基元的速率同时向多个光栅化器提供原语，同时保持每个像素的原始排序。 多个独立的光栅化器单元在一个或多个图形基元上同时执行光栅化，使得能够每个系统时钟渲染多个基元。

公开(公告)号：US20140118379A1

公开(公告)日：2014-05-01

申请号：US14012308

申请日：2013-08-28

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Rouslan DIMITROV ,  Emmett M. KILGARIFF ,  Andrei KHODAKOVSKY

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/601 ,  G06T11/40 ,  G06T15/005 ,  G09G2360/121

Abstract: One embodiment of the present invention includes techniques for adaptively sizing cache tiles in a graphics system. A device driver associated with a graphics system sets a cache tile size associated with a cache tile to a first size. The detects a change from a first render target configuration that includes a first set of render targets to a second render target configuration that includes a second set of render targets. The device driver sets the cache tile size to a second size based on the second render target configuration. One advantage of the disclosed approach is that the cache tile size is adaptively sized, resulting in fewer cache tiles for less complex render target configurations. Adaptively sizing cache tiles leads to more efficient processor utilization and reduced power requirements. In addition, a unified L2 cache tile allows dynamic partitioning of cache memory between cache tile data and other data.

Abstract translation: 本发明的一个实施例包括用于在图形系统中自动调整高速缓存块的尺寸的技术。 与图形系统相关联的设备驱动程序将与高速缓存平铺相关联的高速缓存平铺大小设置为第一大小。 检测从包括第一组渲染目标的第一渲染目标配置到包括第二组渲染目标的第二渲染目标配置的改变。 设备驱动程序基于第二渲染目标配置将高速缓存磁贴大小设置为第二大小。 所公开方法的一个优点是缓存片大小自适应地大小，导致用于较不复杂的渲染目标配置的较少高速缓存片。 自动调整高速缓存片段的大小可以提高处理器利用率并降低功耗。 另外，一个统一的L2高速缓存块允许缓存区块数据和其他数据之间的高速缓冲存储器的动态分区。

公开(公告)号：US20150206511A1

公开(公告)日：2015-07-23

申请号：US14162591

申请日：2014-01-23

Applicant: NVIDIA Corporation

Inventor： Emmett M. KILGARIFF

IPC: G09G5/36 ,  H04N19/423 ,  G06T1/20

CPC classification number: G09G5/363 ,  G06T1/20 ,  G09G5/36 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2350/00 ,  G09G2360/06 ,  G09G2360/125 ,  G09G2360/127 ,  H04N19/423

Abstract: A graphics system includes an integrated graphics processor and a discrete graphics processing unit. An intra-system bus coupled data from the discrete graphics processing unit to the integrated graphics processor. In a high performance mode the discrete graphics processing unit is used to render frames. Compression techniques are used to aid in the data transfer over an intra-system bus interface.

Abstract translation: 图形系统包括集成图形处理器和独立图形处理单元。 系统内总线将数据从分立图形处理单元耦合到集成图形处理器。 在高性能模式下，离散图形处理单元用于渲染帧。 压缩技术用于帮助通过系统内总线接口进行数据传输。

公开(公告)号：US20150097845A1

公开(公告)日：2015-04-09

申请号：US14046850

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Cynthia Ann Edgeworth ALLISON ,  Joseph CAVANAUGH ,  Dale L. KIRKLAND ,  Emmett M. KILGARIFF

IPC: G06F9/38 ,  G06T15/80 ,  G06T15/00 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from a world-space pipeline, and transmitting the first plurality of graphics primitives to a screen-space pipeline for processing while a tiling function is enabled. The technique further includes storing, in the buffer, a second plurality of graphics primitives and a second plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the tiling function should be disabled and that the second plurality of graphics primitives should be flushed from the buffer, and transmitting the second plurality of graphics primitives to the screen-space pipeline for processing while the tiling function is disabled.

Abstract translation: 本发明的一个实施例包括一种在基于瓦片的架构中处理图形基元的技术。 该技术包括在缓冲器中存储从世界空间流水线接收的第一多个图形基元和第一多个状态束，并且将第一多个图形基元发送到屏幕空间管线以进行平铺功能 启用。 该技术还包括在缓冲器中存储从世界空间管道接收的第二多个图形基元和第二多个状态束。 该技术还包括基于第一条件来确定应该禁用平铺函数，并且应该从缓冲器刷新第二多个图形基元，并且将第二多个图形基元发送到屏幕空间管线用于处理 而平铺功能被禁用。

公开(公告)号：US20140118352A1

公开(公告)日：2014-05-01

申请号：US13927026

申请日：2013-06-25

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Emmett M. KILGARIFF

IPC: G06T15/50

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a graphics subsystem for processing multi-sample anti-aliasing work. The graphics subsystem includes a cache unit, a tiling unit, and a screen-space pipeline coupled to the cache unit and to the tiling unit. The tiling unit is configured to organize multi-sample anti-aliasing commands into cache tile batches. The screen-space pipeline includes a pixel shader and a raster operations unit, and receives cache tile batches from the tiling unit. The pixel shader is configured to generate sample data based on a set of primitives and to generate resolved data based on the sample data. The raster operations unit is configured to store the sample data in the cache unit and to invalidate the sample data after the pixel shader generates the resolved data.

Abstract translation: 本发明的一个实施例包括用于处理多样本抗锯齿工作的图形子系统。 图形子系统包括缓存单元，平铺单元以及耦合到高速缓存单元和平铺单元的屏幕空间流水线。 平铺单元被配置为将多样本抗锯齿命令组织到高速缓存块批次中。 屏幕空间管道包括像素着色器和光栅操作单元，并且从平铺单元接收缓存片批次。 像素着色器被配置为基于一组图元生成样本数据，并且基于样本数据生成解析数据。 光栅操作单元被配置为将样本数据存储在高速缓存单元中，并且在像素着色器生成解析数据之后使样本数据无效。

公开(公告)号：US20140184617A1

公开(公告)日：2014-07-03

申请号：US13728881

申请日：2012-12-27

Applicant: NVIDIA CORPORATION

Inventor： Gregory Scott PALMER ,  Ziyad S. HAKURA ,  Emmett M. KILGARIFF ,  Dale L. KIRKLAND ,  Lacky V. SHAH

IPC: G06F9/38

CPC classification number: G06T1/20

Abstract: One embodiment of the present invention sets forth a technique for mid-primitive execution preemption. When preemption is initiated no new instructions are issued, in-flight instructions progress to an execution unit boundary, and the execution state is unloaded from the processing pipeline. The execution units within the processing pipeline, including the coarse rasterization unit complete execution of in-flight instructions and become idle. However, rasterization of a triangle may be preempted at a coarse raster region boundary. The amount of context state to be stored is reduced because the execution units are idle. Preempting at the mid-primitive level during rasterization reduces the time from when preemption is initiated to when another process can execute because the entire triangle is not rasterized.

Abstract translation: 本发明的一个实施例提出了一种用于中原始执行抢占的技术。 当启动抢占时，不会发出新的指令，飞行中的指令进行到执行单位边界，执行状态从处理流水线中卸载。 处理流水线内的执行单元，包括粗略光栅化单元，完成飞行中指令的执行并变为空闲状态。 然而，在粗略的栅格区域边界处，可以抢占三角形的光栅化。 由于执行单元是空闲的，因此减少了要存储的上下文状态量。 在光栅化过程中，在中等原始级别抢占时间减少了从抢占启动到另一个进程可以执行的时间，因为整个三角形不被光栅化。

公开(公告)号：US20140160126A1

公开(公告)日：2014-06-12

申请号：US14094567

申请日：2013-12-02

Applicant: NVIDIA CORPORATION

Inventor： Justin S. LEGAKIS ,  Emmett M. KILGARIFF ,  Michael C. SHEBANOW

IPC: G06T17/20

CPC classification number: G06T17/20 ,  G06T15/005

Abstract: A system and method for performing tessellation of three-dimensional surface patches performs some tessellation operations using programmable processing units and other tessellation operations using fixed function units with limited precision. (u,v) parameter coordinates for each vertex are computed using fixed function units to offload programmable processing engines. The (u,v) computation is a symmetric operation and is based on integer coordinates of the vertex, tessellation level of detail values, and a spacing mode.

Abstract translation: 用于执行三维表面贴片的细分的系统和方法使用具有有限精度的固定功能单元，使用可编程处理单元和其他镶嵌操作来执行一些镶嵌操作。 （u，v）使用固定功能单元计算每个顶点的参数坐标，以卸载可编程处理引擎。 （u，v）计算是对称运算，并且基于顶点的整数坐标，细节值的细分级别和间隔模式。