公开(公告)号：US09407427B2

公开(公告)日：2016-08-02

申请号：US13772157

申请日：2013-02-20

Applicant: NVIDIA CORPORATION

Inventor： Gregory Kodani ,  Guatam Bhatia ,  Peter C. Mills

IPC: H04L7/00 ,  H03L7/00 ,  H04L5/14 ,  G06F13/42 ,  H04L7/033

CPC classification number: H04L7/0083 ,  G06F13/4295 ,  H03L7/00 ,  H04L5/1423 ,  H04L7/0025 ,  H04L7/033

Abstract: A first transceiver is configured to transmit a first data signal to a second transceiver across a communication link. The second transceiver maintains clock data recovery (CDR) lock with the first signal by adjusting a sampling clock configured to sample the first data signal. When the communication link reverses directions, the second transceiver is configured to transmit a second data signal to the first transceiver with the phase of that second data signal adjusted based on the adjustments made to the sampling clock.

Abstract translation: 第一收发器被配置为通过通信链路将第一数据信号发送到第二收发器。 第二收发器通过调整被配置为采样第一数据信号的采样时钟来保持与第一信号的时钟数据恢复（CDR）锁定。 当通信链路反转方向时，第二收发器被配置为将第二数据信号发送到第一收发器，其中该第二数据信号的相位根据对采样时钟的调整而被调整。