公开(公告)号：US09184907B2

公开(公告)日：2015-11-10

申请号：US13730556

申请日：2012-12-28

Applicant: NVIDIA Corporation

Inventor： Peter C. Mills ,  Gautam Bhatia

IPC: H04L7/00

CPC classification number: H04L7/0037 ,  H04L7/0337

Abstract: One embodiment provides a data-receiving device component comprising a phase shifter, timer logic, and control logic. The phase shifter is configured to release a train of clock pulses with a controlled phase shift. The timer logic is configured to receive data from a data-sending device, and for each transition of the data received, to determine whether a clock pulse from the train is early or late with respect to the transition, and to tally the late clock pulses relative to the early clock pulses. The control logic, operatively coupled to the phase shifter and to the timer logic, is configured to incrementally advance the phase shift when the late clock pulses outnumber the early clock pulses by a non-integer power of two.

Abstract translation: 一个实施例提供了包括移相器，定时器逻辑和控制逻辑的数据接收设备组件。 移相器被配置为释放具有受控相移的一串时钟脉冲。 定时器逻辑被配置为从数据发送设备接收数据，并且对于接收到的数据的每个转换，以确定来自列车的时钟脉冲是否相对于转换的早期或晚期，并且对晚时钟脉冲进行计数 相对于早期的时钟脉冲。 可操作地耦合到移相器和定时器逻辑的控制逻辑被配置为当后期时钟脉冲超过早期时钟脉冲的非整数倍数为2时，递增地推进相移。

公开(公告)号：US20140164847A1

公开(公告)日：2014-06-12

申请号：US13707396

申请日：2012-12-06

Applicant: NVIDIA CORPORATION

Inventor： Peter C. Mills ,  Gautam Bhatia

IPC: G06F11/34

CPC classification number: G06F11/25

Abstract: One embodiment includes receiving a data signal transmitted to the processing unit, analyzing the data signal and generating feedback information related to the data signal, and capturing the data signal via a write enable during a plurality of clock cycles specified by a programmable controller included within the processing unit. One advantage of the disclosed technique is that the programmable controller can be used to set the capture window for one or more hardwired triggers included within the processing unit. Further, the programmable controller is able to set up additional triggers that separate and apart from the hardwired triggers included within the processing unit and set the capture window for those triggers. Thus, the disclosed technique provides a highly flexible and adaptive approach for capturing and storing on-chip data and feedback information that can be analyzed later when performing diagnostic and debugging operations.

Abstract translation: 一个实施例包括接收发送到处理单元的数据信号，分析数据信号并产生与数据信号相关的反馈信息，以及在由包括在该数据信号中的可编程控制器指定的多个时钟周期期间通过写使能来捕获数据信号 处理单元。 所公开的技术的一个优点是可编程控制器可以用于设置包括在处理单元内的一个或多个硬连线触发器的捕获窗口。 此外，可编程控制器能够设置与包括在处理单元内的硬连线触发器分离和分开的附加触发器，并为这些触发器设置捕获窗口。 因此，所公开的技术提供了用于捕获和存储片上数据和反馈信息的高度灵活和自适应的方法，其可以在执行诊断和调试操作时稍后分析。

公开(公告)号：US11720440B2

公开(公告)日：2023-08-08

申请号：US17373678

申请日：2021-07-12

Applicant: NVIDIA CORPORATION

Inventor： Naveen Cherukuri ,  Saurabh Hukerikar ,  Paul Racunas ,  Nirmal Raj Saxena ,  David Charles Patrick ,  Yiyang Feng ,  Abhijeet Ghadge ,  Steven James Heinrich ,  Adam Hendrickson ,  Gentaro Hirota ,  Praveen Joginipally ,  Vaishali Kulkarni ,  Peter C. Mills ,  Sandeep Navada ,  Manan Patel ,  Liang Yin

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/1018 ,  G06F11/14 ,  G06F12/1027

CPC classification number: G06F11/1016 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1407 ,  G06F12/1018 ,  G06F12/1027

Abstract: Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.

公开(公告)号：US20130138926A1

公开(公告)日：2013-05-30

申请号：US13674890

申请日：2012-11-12

Applicant: NVIDIA CORPORATION

Inventor： Brett W. Coon ,  John R. Nickolls ,  Lars Nyland ,  Peter C. Mills ,  John Erik Lindholm

IPC: G06F9/38

CPC classification number: G06F9/38 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3851 ,  G06F9/3885

Abstract: An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.

Abstract translation: 间接分支指令将地址寄存器作为参数，以便为单指令多线程（SIMT）处理器架构提供间接函数调用能力。 间接分支指令用于实现间接函数调用，虚函数调用和switch语句，以提高处理性能，与使用连续的测试和分支链相比。

公开(公告)号：US09639365B2

公开(公告)日：2017-05-02

申请号：US13674890

申请日：2012-11-12

Applicant: NVIDIA Corporation

Inventor： Brett W. Coon ,  John R. Nickolls ,  Lars Nyland ,  Peter C. Mills ,  John Erik Lindholm

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/38 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3851 ,  G06F9/3885

Abstract: An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.

公开(公告)号：US20140185633A1

公开(公告)日：2014-07-03

申请号：US13730556

申请日：2012-12-28

Applicant: NVIDIA CORPORATION

Inventor： Peter C. Mills ,  Gautam Bhatia

IPC: H04L7/00

CPC classification number: H04L7/0037 ,  H04L7/0337

Abstract: One embodiment provides a data-receiving device component comprising a phase shifter, timer logic, and control logic. The phase shifter is configured to release a train of clock pulses with a controlled phase shift. The timer logic is configured to receive data from a data-sending device, and for each transition of the data received, to determine whether a clock pulse from the train is early or late with respect to the transition, and to tally the late clock pulses relative to the early clock pulses. The control logic, operatively coupled to the phase shifter and to the timer logic, is configured to incrementally advance the phase shift when the late clock pulses outnumber the early clock pulses by a non-integer power of two.

Abstract translation: 一个实施例提供了包括移相器，定时器逻辑和控制逻辑的数据接收设备组件。 移相器被配置为释放具有受控相移的一串时钟脉冲。 定时器逻辑被配置为从数据发送设备接收数据，并且对于接收到的数据的每个转换，以确定来自列车的时钟脉冲是否相对于转换的早期或晚期，并且对晚时钟脉冲进行计数 相对于早期的时钟脉冲。 可操作地耦合到移相器和定时器逻辑的控制逻辑被配置为当后期时钟脉冲超过早期时钟脉冲的非整数倍数为2时，递增地推进相移。

公开(公告)号：US10423424B2

公开(公告)日：2019-09-24

申请号：US13631685

申请日：2012-09-28

Applicant: NVIDIA Corporation

Inventor： Lincoln G. Garlick ,  Philip Browning Johnson ,  Rafal Zboinski ,  Jeff Tuckey ,  Samuel H. Duncan ,  Peter C. Mills

IPC: G06F9/38

Abstract: Techniques are disclosed for performing an auxiliary operation via a compute engine associated with a host computing device. The method includes determining that the auxiliary operation is directed to the compute engine, and determining that the auxiliary operation is associated with a first context comprising a first set of state parameters. The method further includes determining a first subset of state parameters related to the auxiliary operation based on the first set of state parameters. The method further includes transmitting the first subset of state parameters to the compute engine, and transmitting the auxiliary operation to the compute engine. One advantage of the disclosed technique is that surface area and power consumption are reduced within the processor by utilizing copy engines that have no context switching capability.

公开(公告)号：US09407427B2

公开(公告)日：2016-08-02

申请号：US13772157

申请日：2013-02-20

Applicant: NVIDIA CORPORATION

Inventor： Gregory Kodani ,  Guatam Bhatia ,  Peter C. Mills

IPC: H04L7/00 ,  H03L7/00 ,  H04L5/14 ,  G06F13/42 ,  H04L7/033

CPC classification number: H04L7/0083 ,  G06F13/4295 ,  H03L7/00 ,  H04L5/1423 ,  H04L7/0025 ,  H04L7/033

Abstract: A first transceiver is configured to transmit a first data signal to a second transceiver across a communication link. The second transceiver maintains clock data recovery (CDR) lock with the first signal by adjusting a sampling clock configured to sample the first data signal. When the communication link reverses directions, the second transceiver is configured to transmit a second data signal to the first transceiver with the phase of that second data signal adjusted based on the adjustments made to the sampling clock.

Abstract translation: 第一收发器被配置为通过通信链路将第一数据信号发送到第二收发器。 第二收发器通过调整被配置为采样第一数据信号的采样时钟来保持与第一信号的时钟数据恢复（CDR）锁定。 当通信链路反转方向时，第二收发器被配置为将第二数据信号发送到第一收发器，其中该第二数据信号的相位根据对采样时钟的调整而被调整。