公开(公告)号：US09417875B2

公开(公告)日：2016-08-16

申请号：US14025482

申请日：2013-09-12

Applicant: NVIDIA Corporation

Inventor： Brian Fahs ,  Ming Y. Siu ,  Brett W. Coon ,  John R. Nickolls ,  Lars Nyland

IPC: G06F9/30 ,  G06F15/00 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/522 ,  G06F8/458 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3851

Abstract: One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.

公开(公告)号：US20130138926A1

公开(公告)日：2013-05-30

申请号：US13674890

申请日：2012-11-12

Applicant: NVIDIA CORPORATION

Inventor： Brett W. Coon ,  John R. Nickolls ,  Lars Nyland ,  Peter C. Mills ,  John Erik Lindholm

IPC: G06F9/38

CPC classification number: G06F9/38 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3851 ,  G06F9/3885

Abstract: An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.

Abstract translation: 间接分支指令将地址寄存器作为参数，以便为单指令多线程（SIMT）处理器架构提供间接函数调用能力。 间接分支指令用于实现间接函数调用，虚函数调用和switch语句，以提高处理性能，与使用连续的测试和分支链相比。

公开(公告)号：US10365930B2

公开(公告)日：2019-07-30

申请号：US15583258

申请日：2017-05-01

Applicant: NVIDIA Corporation

Inventor： John R. Nickolls ,  Brett W. Coon ,  Michael C. Shebanow

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/121 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0871

Abstract: A technique for managing a parallel cache hierarchy that includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.

公开(公告)号：US09830197B2

公开(公告)日：2017-11-28

申请号：US15238428

申请日：2016-08-16

Applicant: NVIDIA CORPORATION

Inventor： Brian Fahs ,  Ming Y Siu ,  Brett W. Coon ,  John R. Nickolls ,  Lars Nyland

IPC: G06F9/30 ,  G06F9/52 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F9/522 ,  G06F8/458 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3851

Abstract: One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.

公开(公告)号：US09639365B2

公开(公告)日：2017-05-02

申请号：US13674890

申请日：2012-11-12

Applicant: NVIDIA Corporation

Inventor： Brett W. Coon ,  John R. Nickolls ,  Lars Nyland ,  Peter C. Mills ,  John Erik Lindholm

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/38 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3851 ,  G06F9/3885

Abstract: An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.