公开(公告)号：US20230359560A1

公开(公告)日：2023-11-09

申请号：US17736557

申请日：2022-05-04

Applicant: NVIDIA CORPORATION

Inventor： Michael FETTERMAN ,  Steven James HEINRICH ,  Shirish GADRE

IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/0877 ,  G06F9/38

CPC classification number: G06F12/0811 ,  G06F12/084 ,  G06F12/0877 ,  G06F9/3816

Abstract: Various embodiments include a system for managing cache memory in a computing system. The system includes a sectored cache memory that provides a mechanism for sharing sectors in a cache line among multiple cache line allocations. Traditionally, different cache line allocations are assigned to different cache lines in the cache memory. Further, cache line allocations may not use all of the sectors of the cache line, leading to low utilization of the cache memory. With the present techniques, multiple cache lines share the same cache line, leading to improved cache memory utilization relative to prior techniques. Further, sectors of cache allocations can be assigned to reduce data bank conflicts when accessing cache memory. Reducing such data bank conflicts can result in improved memory access performance, even when cache lines are shared with multiple allocations.

公开(公告)号：US20230305957A1

公开(公告)日：2023-09-28

申请号：US17702458

申请日：2022-03-23

Applicant: NVIDIA CORPORATION

Inventor： Michael FETTERMAN ,  Shirish GADRE ,  Steven James HEINRICH ,  Martin STICH ,  Liang YIN

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Various embodiments include techniques for managing cache memory in a computing system. The computing system includes a sectored cache memory that provides a mechanism for software applications to directly invalidate data items stored in the cache memory on a sector-by-sector basis, where a sector is smaller than a cache line. When all sectors in a cache line have been invalidated, the cache line is implicitly invalidated, freeing the cache line to be reallocated for other purposes. In cases where the data items to be invalidated can be aligned to sector boundaries, the disclosed techniques effectively use status indicators in the cache tag memory to track which sectors, and corresponding data items, have been invalidated by the software application. Thus, the disclosed techniques thereby enable a low-overhead solution for invalidating individual data items that are smaller than a cache line without additional tracking data structures or consuming additional memory transfer bandwidth.

公开(公告)号：US20220392140A1

公开(公告)日：2022-12-08

申请号：US17339603

申请日：2021-06-04

Applicant: NVIDIA CORPORATION

Inventor： Tomas AKENINE-MOLLER ,  Michael FETTERMAN ,  Steven James HEINRICH

IPC: G06T15/04 ,  G06T15/06 ,  G06T15/00

Abstract: Techniques are disclosed herein for interleaving textures. In the disclosed techniques, multiple textures that would otherwise be accessed separately are interleaved into a single, interleaved texture that can be used to access the multiple textures together. The interleaved texture can include alternating blocks from the multiple textures. The interleaved texture can be generated when the multiple textures are being loaded into memory. Further, the interleaved texture can be accessed using multiple texture headers that are associated with different textures in the interleaved texture. Each of texture headers includes a stride indicating the distance between two blocks from a same texture in the interleaved texture.

公开(公告)号：US20210398241A1

公开(公告)日：2021-12-23

申请号：US16910029

申请日：2020-06-23

Applicant: NVIDIA CORPORATION

Inventor： Michael FETTERMAN ,  Shirish GADRE ,  Mark GEBHART ,  Steven J. HEINRICH ,  Ramesh JANDHYALA ,  William NEWHALL ,  Omkar PARANJAPE ,  Stefano PESCADOR ,  Poorna RAO

IPC: G06T1/20 ,  G06F16/245 ,  G06T1/60

Abstract: A texture processing pipeline in a graphics processing unit generates the surface appearance for objects in a computer-generated scene. This texture processing pipeline determines, at multiple stages within the texture processing pipeline, whether texture operations and texture loads may be processed at an accelerated rate. At each stage that includes a decision point, the texture processing pipeline assumes that the current texture operation or texture load can be accelerated unless specific, known information indicates that the texture operation or texture load cannot be accelerated. As a result, the texture processing pipeline increases the number of texture operations and texture loads that are accelerated relative to the number of texture operations and texture loads that are not accelerated.