公开(公告)号：US20210398241A1

公开(公告)日：2021-12-23

申请号：US16910029

申请日：2020-06-23

Applicant: NVIDIA CORPORATION

Inventor： Michael FETTERMAN ,  Shirish GADRE ,  Mark GEBHART ,  Steven J. HEINRICH ,  Ramesh JANDHYALA ,  William NEWHALL ,  Omkar PARANJAPE ,  Stefano PESCADOR ,  Poorna RAO

IPC: G06T1/20 ,  G06F16/245 ,  G06T1/60

Abstract: A texture processing pipeline in a graphics processing unit generates the surface appearance for objects in a computer-generated scene. This texture processing pipeline determines, at multiple stages within the texture processing pipeline, whether texture operations and texture loads may be processed at an accelerated rate. At each stage that includes a decision point, the texture processing pipeline assumes that the current texture operation or texture load can be accelerated unless specific, known information indicates that the texture operation or texture load cannot be accelerated. As a result, the texture processing pipeline increases the number of texture operations and texture loads that are accelerated relative to the number of texture operations and texture loads that are not accelerated.

公开(公告)号：US20210326137A1

公开(公告)日：2021-10-21

申请号：US17363561

申请日：2021-06-30

Applicant: NVIDIA Corporation

Inventor： Andrew KERR ,  Jack CHOQUETTE ,  Xiaogang QIU ,  Omkar PARANJAPE ,  Poornachandra RAO ,  Shirish GADRE ,  Steven J. HEINRICH ,  Manan PATEL ,  Olivier GIROUX ,  Alan KAATZ

IPC: G06F9/30 ,  G06F12/0808 ,  G06F12/0888 ,  G06F9/32 ,  G06F9/38 ,  G06F9/52 ,  G06F9/54

Abstract: A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.

公开(公告)号：US20180322078A1

公开(公告)日：2018-11-08

申请号：US15716461

申请日：2017-09-26

Applicant: NVIDIA Corporation

Inventor： Xiaogang QIU ,  Ronny KRASHINSKY ,  Steven HEINRICH ,  Shirish GADRE ,  John EDMONDSON ,  Jack CHOQUETTE ,  Mark GEBHART ,  Ramesh JANDHYALA ,  Poornachandra RAO ,  Omkar PARANJAPE ,  Michael SIU

IPC: G06F13/28 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/084

Abstract: A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.

公开(公告)号：US20180322077A1

公开(公告)日：2018-11-08

申请号：US15587213

申请日：2017-05-04

Applicant: NVIDIA Corporation

Inventor： Xiaogang QIU ,  Ronny KRASHINSKY ,  Steven HEINRICH ,  Shirish GADRE ,  John EDMONDSON ,  Jack CHOQUETTE ,  Mark GEBHART ,  Ramesh JANDHYALA ,  Poornachandra RAO ,  Omkar PARANJAPE ,  Michael SIU

IPC: G06F13/28 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/084

Abstract: A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.

公开(公告)号：US20220027160A1

公开(公告)日：2022-01-27

申请号：US16940363

申请日：2020-07-27

Applicant: NVIDIA Corporation

Inventor： Michael A. FETTERMAN ,  Mark GEBHART ,  Shirish GADRE ,  Mitchell HAYENGA ,  Steven HEINRICH ,  Ramesh JANDHYALA ,  Raghavan MADHAVAN ,  Omkar PARANJAPE ,  James ROBERTSON ,  Jeff SCHOTTMILLER

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/54 ,  G06F12/084 ,  G06F12/0873

Abstract: In a streaming cache, multiple, dynamically sized tracking queues are employed. Request tracking information is distributed among the plural tracking queues to selectively enable out-of-order memory request returns. A dynamically controlled policy assigns pending requests to tracking queues, providing for example in-order memory returns in some contexts and/or for some traffic and out of order memory returns in other contexts and/or for other traffic.

公开(公告)号：US20200043123A1

公开(公告)日：2020-02-06

申请号：US16053341

申请日：2018-08-02

Applicant: NVIDIA Corporation

Inventor： Rajballav DASH ,  Gregory PALMER ,  Gentaro HIROTA ,  Lacky SHAH ,  Jack CHOQUETTE ,  Emmett KILGARIFF ,  Sriharsha NIVERTY ,  Milton LEI ,  Shirish GADRE ,  Omkar PARANJAPE ,  Lei YANG ,  Rouslan DIMITROV

IPC: G06T1/20 ,  G06F9/38

Abstract: A parallel processing unit (e.g., a GPU), in some examples, includes a hardware scheduler and hardware arbiter that launch graphics and compute work for simultaneous execution on a SIMD/SIMT processing unit. Each processing unit (e.g., a streaming multiprocessor) of the parallel processing unit operates in a graphics-greedy mode or a compute-greedy mode at respective times. The hardware arbiter, in response to a result of a comparison of at least one monitored performance or utilization metric to a user-configured threshold, can selectively cause the processing unit to run one or more compute work items from a compute queue when the processing unit is operating in the graphics-greedy mode, and cause the processing unit to run one or more graphics work items from a graphics queue when the processing unit is operating in the compute-greedy mode. Associated methods and systems are also described.