-
公开(公告)号：US20210390755A1
公开(公告)日：2021-12-16
申请号：US16897745
申请日：2020-06-10
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , James ROBERTSON , Magnus ANDERSSON
Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. The traversal efficiency of such hardware accelerators are improved, for example, by transforming a ray, in hardware, from the ray's coordinate space to two or more coordinate spaces at respective points in traversing the hierarchical acceleration structure. In one example, the hardware accelerator is configured to transform a ray, received from a processor, from the world space to at least one alternate world space and then to an object space in hardware before a corresponding ray-primitive intersection results are returned to the processor. The techniques disclosed herein facilitate the use of additional coordinate spaces to orient acceleration structures in a manner that more efficiently approximate the space occupied by the underlying primitives being ray-traced.
-
Patent Agency Ranking
2.发明公开公开(公告)号：US20240169655A1
公开(公告)日：2024-05-23
申请号：US18420449
申请日：2024-01-23
Applicant: NVIDIA Corporation
Inventor： Greg MUTHLER , Ronald Charles BABICH, JR. , William Parsons NEWHALL, Jr. , Peter NELSON , James ROBERTSON , John BURGESS
CPC classification number: G06T15/06 , G06F9/3877 , G06N5/046 , G06T1/20 , G06T1/60 , G06T17/005
Abstract: In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.
-
公开(公告)号：US20240303906A1
公开(公告)日：2024-09-12
申请号：US18668599
申请日：2024-05-20
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , James ROBERTSON , Magnus ANDERSON
CPC classification number: G06T15/06 , G06F9/5027 , G06T1/20 , G06T15/005 , G06T15/08 , G06T17/10 , G06T2210/12
Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. The traversal efficiency of such hardware accelerators are improved, for example, by transforming a ray, in hardware, from the ray's coordinate space to two or more coordinate spaces at respective points in traversing the hierarchical acceleration structure. In one example, the hardware accelerator is configured to transform a ray, received from a processor, from the world space to at least one alternate world space and then to an object space in hardware before a corresponding ray-primitive intersection results are returned to the processor. The techniques disclosed herein facilitate the use of additional coordinate spaces to orient acceleration structures in a manner that more efficiently approximate the space occupied by the underlying primitives being ray-traced.
-
4.发明申请公开(公告)号：US20200051318A1
公开(公告)日：2020-02-13
申请号：US16101232
申请日：2018-08-10
Applicant: NVIDIA Corporation
Inventor： Greg MUTHLER , Ronald Charles BABICH, JR. , William Parsons NEWHALL, JR. , Peter NELSON , James ROBERTSON , John BURGESS
Abstract: In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.
-
公开(公告)号：US20220027160A1
公开(公告)日：2022-01-27
申请号：US16940363
申请日：2020-07-27
Applicant: NVIDIA Corporation
Inventor： Michael A. FETTERMAN , Mark GEBHART , Shirish GADRE , Mitchell HAYENGA , Steven HEINRICH , Ramesh JANDHYALA , Raghavan MADHAVAN , Omkar PARANJAPE , James ROBERTSON , Jeff SCHOTTMILLER
IPC: G06F9/38 , G06F9/30 , G06F9/54 , G06F12/084 , G06F12/0873
Abstract: In a streaming cache, multiple, dynamically sized tracking queues are employed. Request tracking information is distributed among the plural tracking queues to selectively enable out-of-order memory request returns. A dynamically controlled policy assigns pending requests to tracking queues, providing for example in-order memory returns in some contexts and/or for some traffic and out of order memory returns in other contexts and/or for other traffic.
-
公开(公告)号：US20220165017A1
公开(公告)日：2022-05-26
申请号：US17669430
申请日：2022-02-11
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , James ROBERTSON , Magnus ANDERSON
Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. The traversal efficiency of such hardware accelerators are improved, for example, by transforming a ray, in hardware, from the ray's coordinate space to two or more coordinate spaces at respective points in traversing the hierarchical acceleration structure. In one example, the hardware accelerator is configured to transform a ray, received from a processor, from the world space to at least one alternate world space and then to an object space in hardware before a corresponding ray-primitive intersection results are returned to the processor. The techniques disclosed herein facilitate the use of additional coordinate spaces to orient acceleration structures in a manner that more efficiently approximate the space occupied by the underlying primitives being ray-traced.
-
-
-
-
-
Search Results
6
records
(took 0.015 seconds)
