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    Simplifying power sequencing for integrated circuits
    1.
    发明授权
    Simplifying power sequencing for integrated circuits 有权

    公开(公告)号：US11294441B2

    公开(公告)日：2022-04-05

    申请号：US16912539

    申请日：2020-06-25

    Applicant: NVIDIA CORPORATION

    Inventor： Rajith Mavila ,  Venkata Suresh Perumalla ,  Kwok San Lee

    IPC: G06F1/26 ,  G06F13/40 ,  G06F11/00

    Abstract: In various embodiments, rail decoupling circuits that are powered by an always on voltage rail allow a core voltage rail to power up independently of an I/O voltage rail without jeopardizing I/O pad circuits that are powered by the I/O voltage rail. In an embodiment, when the always on voltage rail is powered-up and a chip reset signal is asserted, the rail decoupling circuits drive control inputs of the I/O pad circuits based on default values. When the chip reset signal is de-asserted, the rail decoupling circuits drive the control inputs of the I/O pad circuits based on signals received from circuits powered by the core voltage rail. Because the rail decoupling circuits maintain control of the I/O pad circuits until the chip-reset is de-asserted, the core voltage rail can power up at any time before the chip-reset signal is de-asserted irrespective of when the I/O voltage rail powers up.

    In system test of chips in functional systems
    3.
    发明授权
    In system test of chips in functional systems 有权

    公开(公告)号：US11408934B2

    公开(公告)日：2022-08-09

    申请号：US16230929

    申请日：2018-12-21

    Applicant: Nvidia Corporation

    Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

    IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G06F11/14 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G01R31/3181 ,  G01R31/3185 ,  G06F11/273

    Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

    IN-SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS
    4.
    发明申请
    IN-SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS 有权

    公开(公告)号：US20220382659A1

    公开(公告)日：2022-12-01

    申请号：US17883199

    申请日：2022-08-08

    Applicant: NVIDIA Corporation

    Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

    IPC: G06F11/27 ,  G06F11/267 ,  G06F11/22

    Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

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