公开(公告)号：US11668750B2

公开(公告)日：2023-06-06

申请号：US17478736

申请日：2021-09-17

Applicant: NVIDIA Corporation

Inventor： Sailendra Chadalavada ,  Venkat Abilash Reddy Nerallapally ,  Jaison Daniel Kurien ,  Bonita Bhaskaran ,  Milind Sonawane ,  Shantanu Sarangi ,  Purnabha Majumder

IPC: G01R31/3177 ,  G06F9/38 ,  G06F1/10 ,  G01R31/28 ,  G06F11/22 ,  G06F15/78 ,  G01R31/317 ,  G01R31/319 ,  G06F1/324 ,  G01R31/3185 ,  G06F1/3237 ,  G06F115/10

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/31922 ,  G01R31/318594 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3237 ,  G06F9/3885 ,  G06F11/2242 ,  G06F15/7864 ,  G06F2115/10

Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

公开(公告)号：US20230089800A1

公开(公告)日：2023-03-23

申请号：US17478736

申请日：2021-09-17

Applicant: NVIDIA Corporation

Inventor： Sailendra Chadalavada ,  Venkat Abilash Reddy Nerallapally ,  Jaison Daniel Kurien ,  Bonita Bhaskaran ,  Milind Sonawane ,  Shantanu Sarangi ,  Purnabha Majumder

IPC: G01R31/3177

Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.