公开(公告)号：US11668750B2

公开(公告)日：2023-06-06

申请号：US17478736

申请日：2021-09-17

Applicant: NVIDIA Corporation

Inventor： Sailendra Chadalavada ,  Venkat Abilash Reddy Nerallapally ,  Jaison Daniel Kurien ,  Bonita Bhaskaran ,  Milind Sonawane ,  Shantanu Sarangi ,  Purnabha Majumder

IPC: G01R31/3177 ,  G06F9/38 ,  G06F1/10 ,  G01R31/28 ,  G06F11/22 ,  G06F15/78 ,  G01R31/317 ,  G01R31/319 ,  G06F1/324 ,  G01R31/3185 ,  G06F1/3237 ,  G06F115/10

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/31922 ,  G01R31/318594 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3237 ,  G06F9/3885 ,  G06F11/2242 ,  G06F15/7864 ,  G06F2115/10

Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

公开(公告)号：US20230089800A1

公开(公告)日：2023-03-23

申请号：US17478736

申请日：2021-09-17

Applicant: NVIDIA Corporation

Inventor： Sailendra Chadalavada ,  Venkat Abilash Reddy Nerallapally ,  Jaison Daniel Kurien ,  Bonita Bhaskaran ,  Milind Sonawane ,  Shantanu Sarangi ,  Purnabha Majumder

IPC: G01R31/3177

Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

公开(公告)号：US20230146920A1

公开(公告)日：2023-05-11

申请号：US17979246

申请日：2022-11-02

Applicant: NVIDIA CORPORATION

Inventor： Bonita Bhaskaran ,  Nithin Valentine ,  Shantanu Sarangi ,  Mahmut Yilmaz ,  Suhas Satheesh ,  Charlie Hwang ,  Tezaswi Raja ,  Kevin Zhou ,  Sailendra Chadalavada ,  Kevin Ye ,  Seyed Nima Mozaffari Mojaveri ,  Kerwin Fu

IPC: G01R31/317 ,  G01R29/26 ,  G01R31/3177

CPC classification number: G01R31/31708 ,  G01R31/31727 ,  G01R29/26 ,  G01R31/31725 ,  G01R31/3177 ,  G01R31/31905

Abstract: Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.