公开(公告)号：US20230317707A1

公开(公告)日：2023-10-05

申请号：US18090708

申请日：2022-12-29

Applicant: NVIDIA Corporation

Inventor： Zhen Jia ,  Xiuzhuang Yang ,  Jing Guo ,  Yuqi Cui

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L23/367 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/5386 ,  H01L23/49816 ,  H01L23/5384 ,  H01L25/16 ,  H01L23/3672 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/4853 ,  H01L25/50

Abstract: An integrated circuit package including a die substrate having a first and second die surfaces, a die high voltage input power connection in the die substrate to receive a high voltage input power and transmit the high voltage input power to a high voltage power trace on the first die surface, a power converter module on the first die surface and electrically connected to the high voltage power trace to convert the high voltage input power to a low voltage output power, a low voltage power trace located on the first die surface and electrically connected to the power converter module to carry the low voltage output power to a circuit die on the first die surface. A method of manufacturing the integrated circuit package and a computer having one or more circuits that include the package is also disclosed.

公开(公告)号：US20220336430A1

公开(公告)日：2022-10-20

申请号：US17591084

申请日：2022-02-02

Applicant: Nvidia Corporation

Inventor： Naly Guo ,  Jerry Jia ,  Xiuzhuang Yang ,  Cindy Cui

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L49/02

Abstract: IC package including a substrate having a first surface, a circuit die coupled to the first surface of the substrate, a decoupling capacitor coupled to the first surface of the substrate and a power trace coupled to the first surface of the substrate and connected to the circuit die and to the decoupling capacitor. A method of manufacturing an IC package include providing a substrate providing a substrate having a first surface, forming a power trace on the first surface of the substrate, mounting a circuit die on the first surface, where the circuit die is electrically connected to the power trace and mounting a decoupling capacitor on the first surface of the substrate, where the decoupling capacitor is electrically connected to the power trace and to the circuit die.