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公开(公告)号：US20230139245A1
公开(公告)日：2023-05-04
申请号：US17452875
申请日：2021-10-29
Applicant: NXP B.V.
Inventor： Marcin Grad , Chinmayee Kumari Panigrahi , Maciej Skrobacki
Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.
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公开(公告)号：US12015407B1
公开(公告)日：2024-06-18
申请号：US18163347
申请日：2023-02-02
Applicant: NXP B.V.
Inventor： Chinmayee Kumari Panigrahi , Marcin Grad , Aman Chugh
IPC: H03K19/0175 , H03K3/356 , H03K19/00 , H03K19/003 , H03K19/0185
CPC classification number: H03K3/35613 , H03K19/0008 , H03K19/00361 , H03K19/0175 , H03K19/018528
Abstract: A circuit that includes a level shifter. The level shifter includes a shift path with two transistors coupled in series. The circuit also includes a GIDL detection circuit for detecting GIDL current conditions. The GIDL detection circuit generates a GIDL signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a transistor of the shift path to increase the conductivity of the transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the shift path when the second transistor is nonconductive due to the level shifter being in a low power mode.
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公开(公告)号：US20240195394A1
公开(公告)日：2024-06-13
申请号：US18163347
申请日：2023-02-02
Applicant: NXP B.V.
Inventor： Chinmayee Kumari Panigrahi , Marcin Grad , Aman Chugh
IPC: H03K3/356 , H03K19/003 , H03K19/0185
CPC classification number: H03K3/35613 , H03K19/00361 , H03K19/018528
Abstract: A circuit that includes a level shifter. The level shifter includes a shift path with two transistors coupled in series. The circuit also includes a GIDL detection circuit for detecting GIDL current conditions. The GIDL detection circuit generates a GIDL signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a transistor of the shift path to increase the conductivity of the transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the shift path when the second transistor is nonconductive due to the level shifter being in a low power mode.
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公开(公告)号：US11605626B2
公开(公告)日：2023-03-14
申请号：US17400160
申请日：2021-08-12
Applicant: NXP B.V.
Inventor： Jian Gao , Marcin Grad
Abstract: An ESD protection circuit includes a trigger transistor that is responsive to a detection signal indicating an ESD event. The trigger transistor pulls the voltage of a hold node towards a voltage of a power supply rail in response to the detection signal indicating an ESD event. The ESD protection circuit includes a replica trigger transistor whose leakage current controls current provided to the hold node after the detection signal no longer indicates an ESD event to compensate for leakage current through the trigger transistor.
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公开(公告)号：US20230050770A1
公开(公告)日：2023-02-16
申请号：US17400160
申请日：2021-08-12
Applicant: NXP B.V.
Inventor： Jian Gao , Marcin Grad
Abstract: An ESD protection circuit includes a trigger transistor that is responsive to a detection signal indicating an ESD event. The trigger transistor pulls the voltage of a hold node towards a voltage of a power supply rail in response to the detection signal indicating an ESD event. The ESD protection circuit includes a replica trigger transistor whose leakage current controls current provided to the hold node after the detection signal no longer indicates an ESD event to compensate for leakage current through the trigger transistor.
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Patent Agency Ranking
公开(公告)号：US20200219867A1
公开(公告)日：2020-07-09
申请号：US16239801
申请日：2019-01-04
Applicant: NXP B.V.
Inventor： Marcin Grad , Paul H. Cappon , Taede Smedes
Abstract: An integrated “pull-down” driver circuit (210) is formed with a combination device consisting of an output driver transistor (N1) electrically coupled between a current source circuit (Ns) and the conductive pad, and an ESD bypass transistor (N3) electrically coupled in series with the output driver transistor, where one or more conductive interconnect layers connect the ESD bypass transistor in parallel with the current source circuit so that the ESD bypass transistor is in an off-state during normal operation and is activated to form a parasitic bipolar junction transistor with the output driver transistor to conduct ESD current between a first power supply conductor and the conductive pad during ESD events, and where a complementary integrated “pull-up” driver circuit may be formed with three corresponding PMOS transistors (P1, PS, P3) connected as shown between a second power supply conductor and the conductive pad.
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公开(公告)号：US11855450B2
公开(公告)日：2023-12-26
申请号：US17452875
申请日：2021-10-29
Applicant: NXP B.V.
Inventor： Marcin Grad , Chinmayee Kumari Panigrahi , Maciej Skrobacki
CPC classification number: H02H9/046 , H02H1/0007
Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.
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公开(公告)号：US11804709B2
公开(公告)日：2023-10-31
申请号：US17452875
申请日：2021-10-29
Applicant: NXP B.V.
Inventor： Marcin Grad , Chinmayee Kumari Panigrahi , Maciej Skrobacki
CPC classification number: H02H9/046 , H02H1/0007
Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.
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公开(公告)号：US11251782B1
公开(公告)日：2022-02-15
申请号：US17094284
申请日：2020-11-10
Applicant: NXP B.V.
Inventor： Marcin Grad , Paul Hendrik Cappon , Kiran B. Gopal , Taede Smedes
IPC: H03K3/356 , H01L27/02 , H03K19/0185
Abstract: As disclosed herein, a level shift circuit includes devices that are responsive to an ESD signal for placing those devices in a specific condition in response to the ESD signal indicating an ESD event. In some embodiments, the devices are transistors in current paths that are placed in a condition such that during an ESD event, voltage differentials in the current paths across voltage domain boundaries do not damage the circuitry of the level shift circuit. In some embodiments, some of the same devices that are responsive to the ESD event are also responsive to a signal to that detects the absence of a power supply voltage of one of the domains and places those devices in a condition to disable the level shift circuit if the power supply voltage is not present.
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公开(公告)号：US10892258B2
公开(公告)日：2021-01-12
申请号：US16239801
申请日：2019-01-04
Applicant: NXP B.V.
Inventor： Marcin Grad , Paul H. Cappon , Taede Smedes
Abstract: An integrated “pull-down” driver circuit (210) is formed with a combination device consisting of an output driver transistor (N1) electrically coupled between a current source circuit (Ns) and the conductive pad, and an ESD bypass transistor (N3) electrically coupled in series with the output driver transistor, where one or more conductive interconnect layers connect the ESD bypass transistor in parallel with the current source circuit so that the ESD bypass transistor is in an off-state during normal operation and is activated to form a parasitic bipolar junction transistor with the output driver transistor to conduct ESD current between a first power supply conductor and the conductive pad during ESD events, and where a complementary integrated “pull-up” driver circuit may be formed with three corresponding PMOS transistors (P1, PS, P3) connected as shown between a second power supply conductor and the conductive pad.
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