公开(公告)号：US12191859B2

公开(公告)日：2025-01-07

申请号：US18332042

申请日：2023-06-09

Applicant: NXP B.V.

Inventor： Saurabh Goyal ,  Divya Tripathi ,  Krishna Thakur ,  Deependra Kumar Jain

IPC: H03K3/017 ,  H03K3/03 ,  H03K5/135

Abstract: An integrated circuit including a functional circuit, a tuning circuit, and a control circuit is provided. The functional and control circuits generate an output signal and a digital code, respectively. The tuning circuit tunes the functional circuit based on the digital code to control an attribute of the output signal. The digital code is iteratively adjusted such that the attribute of the output signal is maintained within a predefined range. When the digital code corresponds to a cliff value, the digital code for a subsequent iteration is adjusted by a non-unit offset value such that a difference between the attribute for the cliff value and for the subsequent digital code is within a tolerance limit. The digital code is indicative of coarse and fine parameters, and for each value of the coarse parameter, the cliff value corresponds to the lowest or highest value of the fine parameter.

公开(公告)号：US11581878B1

公开(公告)日：2023-02-14

申请号：US17450403

申请日：2021-10-08

Applicant: NXP B.V.

Inventor： Sanjay Kumar Wadhwa ,  Saurabh Goyal ,  Divya Tripathi

IPC: H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03F3/45 ,  H03K3/356 ,  H03K17/10 ,  H03K5/156

Abstract: A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.

公开(公告)号：US20230361772A1

公开(公告)日：2023-11-09

申请号：US17662086

申请日：2022-05-05

Applicant: NXP B.V.

Inventor： Sanjay Kumar Wadhwa ,  Divya Tripathi ,  Saurabh Goyal ,  Alvin Leng Sun Loke ,  Manish Kumar Upadhyay

IPC: H03K17/687

CPC classification number: H03K17/6871

Abstract: An integrated circuit (IC) includes one or more active transistors and multiple series-coupled dummy transistors. The dummy transistors are coupled between two active transistors and/or at the ends of each active transistor. When the dummy transistors are coupled between two active transistors, apart from two conductive regions that are coupled to two active transistors, each remaining conductive region of the dummy transistors is maintained in a floating state to control a leakage current between the two active transistors. Similarly, when the dummy transistors are coupled at an end of one active transistor, apart from one conductive region that is coupled to the active transistor, each remaining conductive region of the dummy transistors is maintained in the floating state to control a leakage current between the active transistor and the dummy transistors.

公开(公告)号：US11378991B1

公开(公告)日：2022-07-05

申请号：US17304632

申请日：2021-06-23

Applicant: NXP B.V.

Inventor： Saurabh Goyal ,  Sanjay Kumar Wadhwa ,  Divya Tripathi

IPC: G05F1/10 ,  G05F1/46

Abstract: A soft-start circuit for a voltage regulator includes a comparator and a delay circuit. The comparator compares an output voltage, that is generated by the voltage regulator, and a reference voltage to generate a comparison signal. Further, the delay circuit receives the reference voltage and a control signal that is outputted based on the comparison signal, and outputs and provides another reference voltage to the voltage regulator. During a start-up of the voltage regulator, the reference voltage outputted by the delay circuit is a delayed version of the reference voltage received by the delay circuit. Thus, the soft-start circuit mitigates an overshoot of the output voltage during the start-up. Further, on completion of the start-up, the reference voltage outputted by the delay circuit is equal to the reference voltage received by the delay circuit.

公开(公告)号：US20240204757A1

公开(公告)日：2024-06-20

申请号：US18332042

申请日：2023-06-09

Applicant: NXP B.V.

Inventor： Saurabh Goyal ,  Divya Tripathi ,  Krishna Thakur ,  Deependra Kumar Jain

IPC: H03K3/017 ,  H03K3/03 ,  H03K5/135

CPC classification number: H03K3/017 ,  H03K3/0315 ,  H03K5/135

Abstract: An integrated circuit including a functional circuit, a tuning circuit, and a control circuit is provided. The functional and control circuits generate an output signal and a digital code, respectively. The tuning circuit tunes the functional circuit based on the digital code to control an attribute of the output signal. The digital code is iteratively adjusted such that the attribute of the output signal is maintained within a predefined range. When the digital code corresponds to a cliff value, the digital code for a subsequent iteration is adjusted by a non-unit offset value such that a difference between the attribute for the cliff value and for the subsequent digital code is within a tolerance limit. The digital code is indicative of coarse and fine parameters, and for each value of the coarse parameter, the cliff value corresponds to the lowest or highest value of the fine parameter.

公开(公告)号：US11277121B1

公开(公告)日：2022-03-15

申请号：US17161083

申请日：2021-01-28

Applicant: NXP B.V.

Inventor： Saurabh Goyal ,  Divya Tripathi ,  Sanjay Kumar Wadhwa

IPC: H03K17/687 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K3/356 ,  H03K19/003 ,  H03K17/10

Abstract: A level shifter includes a pull-down circuit, a pull-up circuit, a protection circuit, and an output generator. The pull-down circuit is configured to receive input voltages, and generate bias voltages. The input voltages are associated with a voltage domain. The pull-up circuit is configured to receive a supply voltage and generate control voltages. The protection circuit is configured to receive reference voltages, and control the generation of the bias voltages and the control voltages. The output generator is configured to receive at least one of the reference voltages, and at least one of the bias voltages and the control voltages, and generate output voltages that are able to reach minimum and maximum voltage levels of another voltage domain. Further, the output voltages remain unaffected by variations in process, voltage, and temperature.