公开(公告)号：US20190164784A1

公开(公告)日：2019-05-30

申请号：US15825079

申请日：2017-11-28

Applicant: NXP B.V.

Inventor： Siriluck Wongratanaporngoorn ,  Yao Jung Chang ,  Ekapong Tangpattanasaeree ,  Paradee Jitrungruang ,  Pitak Seantumpol

IPC: H01L21/56 ,  H01L21/683 ,  H01L21/768

Abstract: A method for wafer dicing and removing separated integrated circuit (IC) dies from a carrier substrate includes mounting a wafer on a substrate using an adhesive layer, laser scribing the adhesive layer to create defect regions in the adhesive layer, and performing a breaking step to separate the laser-scribed adhesive layer into separated adhesive portions corresponding to the IC dies. For a stealth-dicing (SD) technique, defect regions also are created in the wafer using a laser and the breaking step is an expansion step that simultaneously separates the dies and corresponding portions of adhesive. For a dice-before-grind (DBG) technique, the dies are separated by backside grinding before the breaking step. Efficient adhesive-layer separation is achieved with reduced backside chipping associated with conventional blade dicing.

公开(公告)号：US10607861B2

公开(公告)日：2020-03-31

申请号：US15825079

申请日：2017-11-28

Applicant: NXP B.V.

Inventor： Siriluck Wongratanaporngoorn ,  Yao Jung Chang ,  Ekapong Tangpattanasaeree ,  Paradee Jitrungruang ,  Pitak Seantumpol

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/683 ,  H01L21/67 ,  H01L21/78 ,  B23K26/00

Abstract: A method for wafer dicing and removing separated integrated circuit (IC) dies from a carrier substrate includes mounting a wafer on a substrate using an adhesive layer, laser scribing the adhesive layer to create defect regions in the adhesive layer, and performing a breaking step to separate the laser-scribed adhesive layer into separated adhesive portions corresponding to the IC dies. For a stealth-dicing (SD) technique, defect regions also are created in the wafer using a laser and the breaking step is an expansion step that simultaneously separates the dies and corresponding portions of adhesive. For a dice-before-grind (DBG) technique, the dies are separated by backside grinding before the breaking step. Efficient adhesive-layer separation is achieved with reduced backside chipping associated with conventional blade dicing.

公开(公告)号：US20180226353A1

公开(公告)日：2018-08-09

申请号：US15427010

申请日：2017-02-07

Applicant: NXP B.V.

Inventor： Ekapong Tangpattanasaeree ,  Wiwat Tanwongwan ,  Amornthep Saiyajitara

IPC: H01L23/544 ,  H01L21/48 ,  H01L23/495

CPC classification number: H01L23/544 ,  H01L23/495 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54486

Abstract: A lead frame used in semiconductor device assembly includes first and second opposing planar surfaces. A marking area is defined on the first planar surface. The marking area has a uniform background color that is different from a color of the first planar surface. A mark is formed in the marking area. The background color of the marking area contrasts with a color of the mark such that a clear image of the mark is easily captured with an image sensor. The mark preferably is a two-dimensional (2D) mark made of bumps and represents encoded information. The contrast between the background color and the mark is especially helpful when the lead frame has a roughened surface.

公开(公告)号：US20190252256A1

公开(公告)日：2019-08-15

申请号：US15896090

申请日：2018-02-14

Applicant: NXP B.V.

Inventor： Pimpa Boonyatee ,  Ekapong Tangpattanasaeree ,  Pitak Seantumpol

IPC: H01L21/82 ,  H01L23/498 ,  H01L23/495

CPC classification number: H01L21/82 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49838 ,  H01L23/49866

Abstract: A method of singulating no-lead semiconductor devices assembled on a lead frame array, includes performing first and second laser scribing operations first and second sides of saw streets of the lead frame array, and then cutting between the first and second scribe lines, formed by the scribing operations, with a saw. The finished devices include a notch, formed by the scribing operations, at exposed portions of the device leads. Scribing the saw streets before cutting prevents smearing of the leads and the formation of burrs on the leads.

公开(公告)号：US20190229044A1

公开(公告)日：2019-07-25

申请号：US15878292

申请日：2018-01-23

Applicant: NXP B.V.

Inventor： AMORNTHEP SAIYAJITARA ,  Wiwat Tanwongwan ,  Chanon Suwankasab ,  Ekapong Tangpattanasaeree

IPC: H01L23/495 ,  H01L21/48

Abstract: A lead frame is formed with exposed lead tips. The leads are not attached at their tips to any of a tie bar, a dam bar or an end bar, so when the lead frame is plated, the lead tips are plated. During packaging, after die attach and molding, when the lead frame is cut from the frame assembly, the lead tips are not cut, so the plating remains on the tips. This improves solder joint reliability when the package is mounted on a PCB. The lead frame has connection bars that run parallel to the leads from the tie bar to the end bar. The connection bars provide stability to the leads during wire bonding, but are cut from the lead frame after wire bonding.