公开(公告)号：US20240204052A1

公开(公告)日：2024-06-20

申请号：US18066110

申请日：2022-12-14

Applicant: NXP B.V.

Inventor： Jay Paul John ,  James Albert Kirchgessner

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/1004 ,  H01L29/0817 ,  H01L29/66242 ,  H01L29/7375 ,  H01L29/0649

Abstract: A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region an intrinsic base region, and a lateral base link region disposed between and in contact with each of the extrinsic base region and an intrinsic base region. The extrinsic base region, the lateral base link region, and a portion of the intrinsic base region each may be formed on a passivation layer disposed over an isolation region and a collector region of a substrate of the semiconductor device. The extrinsic base region and a first portion of the lateral base link region may be formed from polycrystalline semiconductor material. The intrinsic base region and a second portion of the lateral base link region may be formed from monocrystalline semiconductor material. The lateral base link region may be formed after formation of the extrinsic base region and the intrinsic base region.

公开(公告)号：US20240178304A1

公开(公告)日：2024-05-30

申请号：US18059849

申请日：2022-11-29

Applicant: NXP B.V.

Inventor： Ljubo Radic ,  Jay Paul John ,  James Albert Kirchgessner ,  Johannes Josephus Theodorus Marinus Donkers

IPC: H01L29/732 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/732 ,  H01L29/1004 ,  H01L29/66234

Abstract: A semiconductor device includes a semiconductor substrate, a collector region formed within the semiconductor substrate in a first semiconductor region having an upper surface and a collector sidewall, a base region disposed over the collector region, a seed region formed over the semiconductor substrate and coupled to the semiconductor substrate outside the base region, an extrinsic base region having an upper surface and formed over the seed region and electrically coupled to the base region, and an emitter region formed over the base region.

公开(公告)号：US20240304707A1

公开(公告)日：2024-09-12

申请号：US18595511

申请日：2024-03-05

Applicant: NXP B.V.

Inventor： Johannes Josephus Theodorus Marinus Donkers ,  Jay Paul John ,  James Albert Kirchgessner ,  Patrick Sebel

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7378 ,  H01L29/0817 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/66242

Abstract: Disclosed is a SiGe, HBT, and method of manufacturing the same, comprising: an n-doped buried collector; a p-doped SiGe base layer, within a layer stack, the layer stack being over and in direct contact with the collector; an n-doped monocrystalline silicon emitter; an epitaxial silicon base contact layer over a second area of the layer stack; a polycrystalline silicon emitter contact layer; an oxide layer over a third area of the layer stack between the first and second areas, wherein the oxide layer and the n-doped monocrystalline silicon emitter are within a window, having sidewalls, in the epitaxial silicon layer; dielectric spacers on the sidewalls of the window and over the oxide layer, and providing electrical isolation between the epitaxial silicon layer and the polycrystalline silicon layer; the epitaxial silicon layer extending beneath the dielectric spacers on the sidewalls of the window.

公开(公告)号：US20240204086A1

公开(公告)日：2024-06-20

申请号：US18067322

申请日：2022-12-16

Applicant: NXP B.V.

Inventor： Jay Paul John ,  James Albert Kirchgessner ,  Johannes Josephus Theodorus Marinus Donkers ,  Ljubo Radic

IPC: H01L29/737 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/66242

Abstract: A semiconductor device includes a semiconductor substrate, a collector region having a first width formed within the semiconductor substrate and an intrinsic base region having a second width, disposed over the collector region, wherein the first width is greater than the second width. An extrinsic base region having an upper surface is formed over the collector region and electrically coupled to the intrinsic base region, wherein the extrinsic base region includes a monocrystalline region coupled to the intrinsic base region and a polycrystalline region coupled to the monocrystalline region. An emitter region is formed over the base region.

公开(公告)号：US20250098189A1

公开(公告)日：2025-03-20

申请号：US18824976

申请日：2024-09-05

Applicant: NXP B.V.

Inventor： Jay Paul John ,  James Albert Kirchgessner ,  Johannes Josephus Theodorus Marinus Donkers ,  Ljubo Radic ,  Patrick Sebel

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/737

Abstract: A bipolar transistor and a method of making a bipolar transistor. The method includes providing a semiconductor substrate having a major surface, one or more layers located beneath the major surface for forming an intrinsic base, and a collector. The method also includes depositing a first oxide layer on the major surface, depositing a second oxide layer on the first oxide layer, and depositing an extrinsic base layer on the second oxide layer. The method further includes forming an emitter window through the extrinsic base layer. The method also includes removing at least a part of the second oxide layer to form a first cavity and forming an initial part of a base link region in the first cavity. The method also includes removing at least a part of the first oxide layer to form a second cavity and filling the second cavity to form a completed base link region.

公开(公告)号：US20240234552A1

公开(公告)日：2024-07-11

申请号：US18527890

申请日：2023-12-04

Applicant: NXP B.V.

Inventor： Jay Paul John ,  Patrick Sebel ,  James Albert Kirchgessner

IPC: H01L29/737 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/165 ,  H01L29/66242

Abstract: Disclosed is a method of manufacturing a silicon bipolar junction transistor device, the method comprising a sequence of steps including: depositing a polysilicon layer over at least a device region; depositing a dielectric layer over the polysilicon layer; patterning a photoresist layer and etching a window in the dielectric layer and the polysilicon layer through an opening in the photoresist layer; etching a SiGe layer stack through the window, to expose a silicon layer thereunder; patterning a further photoresist layer to expose at least the window; and doping the silicon layer by ion implantation through the window to form a base region. A corresponding BJT device is also disclosed.