公开(公告)号：US20130154050A1

公开(公告)日：2013-06-20

申请号：US13687172

申请日：2012-11-28

Applicant: NXP B.V.

Inventor： Piet Wessels ,  Nico Berckmans ,  Khin Hoong Lim ,  Michael John Ben Bolt ,  Jerome Guillaume Anna Dubois ,  Naveen Agrawal ,  Gaurav Singh Bisht ,  Jayaraj Thillaigovindan ,  Jie Liao

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L29/0649

Abstract: Disclosed is an integrated circuit die comprising an active substrate including a plurality of components laterally separated from each other by respective isolation structures, at least some of the isolation structures carrying a further component, wherein the respective portions of the active substrate underneath the isolation structures carrying said further components are electrically insulated from said components. A method of manufacturing such an IC die is also disclosed.

Abstract translation: 公开了一种集成电路管芯，其包括有源衬底，所述有源衬底包括通过相应的隔离结构彼此横向分离的多个部件，所述隔离结构中的至少一些承载另外的部件，其中所述有源衬底的相应部分在所述隔离结构之下承载 所述另外的部件与所述部件电绝缘。 还公开了制造这种IC芯片的方法。

公开(公告)号：US09105687B1

公开(公告)日：2015-08-11

申请号：US14254523

申请日：2014-04-16

Applicant: NXP B.V.

Inventor： Jerome Dubois ,  Piet Wessels ,  Gaurav Singh Bisht ,  Jayaraj Thillaigovindan ,  Eric Ooms ,  Naveen Agrawal

IPC: H01L21/762 ,  H01L21/321 ,  H01L21/306

CPC classification number: H01L21/76235 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/764

Abstract: A method of manufacturing a semiconductor device includes forming a trench that includes a needle defect, depositing a high density plasma oxide over the trench including the needle defect, removing the part of the high density oxide and the liner oxide over the needle defect by applying an oxide etch, and after the step of applying the oxide etch, etching back the needle defect by applying a polysilicon etch.

Abstract translation: 一种制造半导体器件的方法包括形成包括针缺陷的沟槽，在包括针缺陷的沟槽上沉积高密度等离子体氧化物，通过施加一个或多个针孔缺陷来去除部分高密度氧化物和衬垫氧化物 氧化物蚀刻，并且在施加氧化物蚀刻的步骤之后，通过施加多晶硅蚀刻来回蚀针缺陷。

公开(公告)号：US08847347B2

公开(公告)日：2014-09-30

申请号：US13687172

申请日：2012-11-28

Applicant: NXP B.V.

Inventor： Piet Wessels ,  Nico Berckmans ,  Khin Hoong Lim ,  Michael John Ben Bolt ,  Jerome Guillaume Anna Dubois ,  Naveen Agrawal ,  Gaurav Singh Bisht ,  Jayaraj Thillaigovindan ,  Jie Liao

IPC: H01L29/00 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L29/0649

Abstract: Disclosed is an integrated circuit die comprising an active substrate including a plurality of components laterally separated from each other by respective isolation structures, at least some of the isolation structures carrying a further component, wherein the respective portions of the active substrate underneath the isolation structures carrying said further components are electrically insulated from said components. A method of manufacturing such an IC die is also disclosed.

Abstract translation: 公开了一种集成电路管芯，其包括有源衬底，所述有源衬底包括通过相应的隔离结构彼此横向分离的多个部件，所述隔离结构中的至少一些承载另外的部件，其中所述有源衬底的相应部分在所述隔离结构之下承载 所述另外的部件与所述部件电绝缘。 还公开了制造这种IC芯片的方法。