公开(公告)号：US08957500B2

公开(公告)日：2015-02-17

申请号：US13648882

申请日：2012-10-10

Applicant: NXP B.V.

Inventor： Jerôme Guillaume Anna Dubois ,  Piet Wessels

IPC: H01L27/02

CPC classification number: H01G4/40 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y02T10/7022 ,  H01L2924/00

Abstract: A high-voltage metal capacitor with easy integration into existing semiconductor manufacturing processes can provide isolation capacitors up to several kilovolts. The capacitor includes a support layer with internal structure, including a lower place, a bond pad on the support layer, an upper plate disposed on the support layer, the upper plate being arranged above the lower plate, a dielectric layer, at least part of which is between the lower and upper plates, and a passivation layer, at least part of which covers at least part of the upper plate and part of the dielectric layer. A first opening extends from the surface through the passivation and dielectric layers to the lower plate, and a second opening extends from the surface through the passivation layer to the upper plate. A method of manufacturing the capacitor.

Abstract translation: 容易集成到现有半导体制造工艺中的高压金属电容器可以提供高达几千伏的隔离电容。 电容器包括具有内部结构的支撑层，包括下部位置，支撑层上的接合焊盘，设置在支撑层上的上板，上板设置在下板的上方，介电层，至少部分 其位于下板和上板之间，钝化层的至少一部分覆盖上板的一部分和电介质层的一部分。 第一开口从表面延伸穿过钝化层和介电层到下板，第二开口从表面延伸穿过钝化层到上板。 一种制造电容器的方法。

公开(公告)号：US20130154050A1

公开(公告)日：2013-06-20

申请号：US13687172

申请日：2012-11-28

Applicant: NXP B.V.

Inventor： Piet Wessels ,  Nico Berckmans ,  Khin Hoong Lim ,  Michael John Ben Bolt ,  Jerome Guillaume Anna Dubois ,  Naveen Agrawal ,  Gaurav Singh Bisht ,  Jayaraj Thillaigovindan ,  Jie Liao

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L29/0649

Abstract: Disclosed is an integrated circuit die comprising an active substrate including a plurality of components laterally separated from each other by respective isolation structures, at least some of the isolation structures carrying a further component, wherein the respective portions of the active substrate underneath the isolation structures carrying said further components are electrically insulated from said components. A method of manufacturing such an IC die is also disclosed.

Abstract translation: 公开了一种集成电路管芯，其包括有源衬底，所述有源衬底包括通过相应的隔离结构彼此横向分离的多个部件，所述隔离结构中的至少一些承载另外的部件，其中所述有源衬底的相应部分在所述隔离结构之下承载 所述另外的部件与所述部件电绝缘。 还公开了制造这种IC芯片的方法。

公开(公告)号：US09105687B1

公开(公告)日：2015-08-11

申请号：US14254523

申请日：2014-04-16

Applicant: NXP B.V.

Inventor： Jerome Dubois ,  Piet Wessels ,  Gaurav Singh Bisht ,  Jayaraj Thillaigovindan ,  Eric Ooms ,  Naveen Agrawal

IPC: H01L21/762 ,  H01L21/321 ,  H01L21/306

CPC classification number: H01L21/76235 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/764

Abstract: A method of manufacturing a semiconductor device includes forming a trench that includes a needle defect, depositing a high density plasma oxide over the trench including the needle defect, removing the part of the high density oxide and the liner oxide over the needle defect by applying an oxide etch, and after the step of applying the oxide etch, etching back the needle defect by applying a polysilicon etch.

Abstract translation: 一种制造半导体器件的方法包括形成包括针缺陷的沟槽，在包括针缺陷的沟槽上沉积高密度等离子体氧化物，通过施加一个或多个针孔缺陷来去除部分高密度氧化物和衬垫氧化物 氧化物蚀刻，并且在施加氧化物蚀刻的步骤之后，通过施加多晶硅蚀刻来回蚀针缺陷。

公开(公告)号：US08847347B2

公开(公告)日：2014-09-30

申请号：US13687172

申请日：2012-11-28

Applicant: NXP B.V.

Inventor： Piet Wessels ,  Nico Berckmans ,  Khin Hoong Lim ,  Michael John Ben Bolt ,  Jerome Guillaume Anna Dubois ,  Naveen Agrawal ,  Gaurav Singh Bisht ,  Jayaraj Thillaigovindan ,  Jie Liao

IPC: H01L29/00 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L29/0649

Abstract: Disclosed is an integrated circuit die comprising an active substrate including a plurality of components laterally separated from each other by respective isolation structures, at least some of the isolation structures carrying a further component, wherein the respective portions of the active substrate underneath the isolation structures carrying said further components are electrically insulated from said components. A method of manufacturing such an IC die is also disclosed.

Abstract translation: 公开了一种集成电路管芯，其包括有源衬底，所述有源衬底包括通过相应的隔离结构彼此横向分离的多个部件，所述隔离结构中的至少一些承载另外的部件，其中所述有源衬底的相应部分在所述隔离结构之下承载 所述另外的部件与所述部件电绝缘。 还公开了制造这种IC芯片的方法。