公开(公告)号：US20190115340A1

公开(公告)日：2019-04-18

申请号：US15783232

申请日：2017-10-13

Applicant: NXP B.V.

Inventor： Jan Claes ,  Stephen John Sque ,  Maarten Jacobus Swanenberg ,  Da-Wei Lai

IPC: H01L27/02 ,  H01L27/07 ,  H01L29/10 ,  H01L29/735

CPC classification number: H01L27/0277 ,  H01L27/0259 ,  H01L27/0705 ,  H01L29/1008 ,  H01L29/735

Abstract: Various embodiments are directed to electrostatic discharge (ESD) protection apparatus comprising a bipolar junction transistor (BJT) having terminals, a field-effect transistor (FET) having terminals, and a common base region connected to a recombination region. The BJT and the FET are integrated with one another and include a common region that is shared by the BJT and the FET. The BJT and FET collectively bias the common base region and prevent triggering of the BJT by causing a potential of the common base region to follow a potential of one of the terminals of the BJT in response to an excessive but tolerable non-ESD voltage change at one or more of the terminals.

公开(公告)号：US10177243B1

公开(公告)日：2019-01-08

申请号：US15626278

申请日：2017-06-19

Applicant: NXP B.V.

Inventor： Dimitar Milkov Dochev ,  Arnold Benedictus Van Der Wal ,  Maarten Jacobus Swanenberg

IPC: H03K17/687 ,  H01L29/66 ,  H01L29/78

Abstract: Described herein is an N type extended drain transistor formed from a semiconductor on insulator (SOI) wafer. The transistor has a buried P type region formed by the selective implantation of P type dopants in a semiconductor layer of the wafer at a location directly below a drift region of the transistor. The transistor also includes a source located in a P well region and a drain. The buried P type region is in electrical contact with the P well region. The N type drift region, the source, and the drain are also located in a portion of the semiconductor layer surrounded by dielectric isolation. A buried dielectric layer located below the portion of the semiconductor layer electrically isolates the portion of the semiconductor layer from a semiconductor substrate located below the buried dielectric layer.

公开(公告)号：US10475783B2

公开(公告)日：2019-11-12

申请号：US15783232

申请日：2017-10-13

Applicant: NXP B.V.

Inventor： Jan Claes ,  Stephen John Sque ,  Maarten Jacobus Swanenberg ,  Da-Wei Lai

IPC: H01L27/02 ,  H01L29/735 ,  H01L29/10 ,  H01L27/07

Abstract: Various embodiments are directed to electrostatic discharge (ESD) protection apparatus comprising a bipolar junction transistor (BJT) having terminals, a field-effect transistor (FET) having terminals, and a common base region connected to a recombination region. The BJT and the FET are integrated with one another and include a common region that is shared by the BJT and the FET. The BJT and FET collectively bias the common base region and prevent triggering of the BJT by causing a potential of the common base region to follow a potential of one of the terminals of the BJT in response to an excessive but tolerable non-ESD voltage change at one or more of the terminals.

公开(公告)号：US20230117505A1

公开(公告)日：2023-04-20

申请号：US17505700

申请日：2021-10-20

Applicant: NXP B.V.

Inventor： Maarten Jacobus Swanenberg

IPC: H03K17/687

Abstract: A circuit comprising a cascode device comprising a field effect transistor. The field effect transistor includes a common body region. The field effect transistor also includes a plurality of source regions. The source regions form inputs of the cascode device. Each source region of the plurality of source regions is separated from each other source region of the plurality of source regions by the common body region. The field effect transistor further includes a common gate. The field effect transistor also includes a common drain region. The common drain region forms an output of the cascode device. The circuit may further include a plurality of groups of one or more current sources each group coupled to a respective one of the inputs of the cascode device, and a current output coupled to the output of the cascode device. A method of operating a current source circuit.

公开(公告)号：US20140375377A1

公开(公告)日：2014-12-25

申请号：US14279497

申请日：2014-05-16

Applicant: NXP B.V.

Inventor： Rob Van Dalen ,  Maarten Jacobus Swanenberg ,  Inesz Emmerik-Weijland

IPC: H01L29/74 ,  H03K17/72 ,  H01L27/15

CPC classification number: H01L29/7408 ,  H01L27/153 ,  H01L29/0839 ,  H01L29/7412 ,  H01L29/7428 ,  H03K17/72

Abstract: A thyristor is disclosed comprising: a first region of a first conductivity type; a second region of a second conductivity type and adjoining the first region; a third region of the first conductivity type and adjoining the second region; a fourth region of the second conductivity type and comprising a first segment and a second segment separate from the first segment, the first segment and second segment each adjoining the third region; a first contact adjoining the first region; a second contact adjoining the first segment; and a trigger contact adjoining the second segment and separate from the second contact.Methods of triggering such a thyristor are also disclosed, as are circuits utilising one or more such thyristors.

Abstract translation: 公开了一种晶闸管，包括：第一导电类型的第一区域; 第二导电类型的第二区域并与第一区域邻接; 所述第一导电类型的第三区域和所述第二区域相邻; 所述第二导电类型的第四区域包括与所述第一段分离的第一段和第二段，所述第一段和第二段各自邻接所述第三区; 邻接第一区域的第一接触; 邻接所述第一段的第二接触; 以及与第二段相邻并且与第二接触分离的触发器触点。 还公开了触发这种晶闸管的方法，以及利用一个或多个这种晶闸管的电路。