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公开(公告)号：US20220393851A1
公开(公告)日：2022-12-08
申请号：US17662918
申请日：2022-05-11
Applicant: NXP B.V.
Abstract: Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader. The card clock recovery system has: a phase lock loop having: a phase/frequency detector, which is configured to receive a reference signal provided at an RX port of a matching network during a receiving mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmission mode of the NFC transceiver, to receive a loop feedback signal, and to provide a phase error signal that represents a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal that is derived from the phase error signal, and to provide a filtered corrected phase error signal; a controllable oscillator, which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal, which is provided as the card clock generation control signal to a card clock generation unit of an NFC card transceiver, and as the loop feedback signal, via the loop feedback line, to the phase/frequency detector. The card clock recovery system further has a phase offset correction unit, which is configured to receive the phase error signal provided by the phase/frequency detector and to provide the corrected phase error signal to the loop filter, and which has a phase error sampling unit, a phase offset computation unit, and a phase subtractor unit.
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Patent Agency Ranking
公开(公告)号：US10346732B2
公开(公告)日：2019-07-09
申请号：US15842871
申请日：2017-12-14
Applicant: NXP B.V.
Inventor： Melaine Philip , Olivier Susplugas
Abstract: A RF transceiver for RF communication with a further RF transceiver is described. The RF transceiver comprises a RF transmitter; a clock generator coupled to the RF transmitter, the clock generator comprising a crystal oscillator circuit including an amplifier, a distance monitor configured to monitor the distance between the RF transceiver and the further RF transceiver; a controller coupled to the distance monitor and the clock generator. The controller is configured to vary the crystal oscillator swing amplitude dependent on the distance between the RF transceiver and the further RF transceiver.
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公开(公告)号：US20180165560A1
公开(公告)日：2018-06-14
申请号：US15842871
申请日：2017-12-14
Applicant: NXP B.V.
Inventor： Melaine Philip , Olivier Susplugas
CPC classification number: G06K19/0705 , G06K19/0712 , H04B5/0031 , H04B5/0056 , H04B5/02
Abstract: A RF transceiver for RF communication with a further RF transceiver is described. The RF transceiver comprises a RF transmitter; a clock generator coupled to the RF transmitter, the clock generator comprising a crystal oscillator circuit including an amplifier, a distance monitor configured to monitor the distance between the RF transceiver and the further RF transceiver; a controller coupled to the distance monitor and the clock generator. The controller is configured to vary the crystal oscillator swing amplitude dependent on the distance between the RF transceiver and the further RF transceiver.
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公开(公告)号：US11979157B2
公开(公告)日：2024-05-07
申请号：US18061674
申请日：2022-12-05
Applicant: NXP B.V.
Inventor： Stefano Dal Toso , Olivier Susplugas
CPC classification number: H03K3/35613 , G06F1/06 , G06F1/08 , H03K5/2481
Abstract: It is described a signal converter device (100) for converting a single-ended signal to a differential signal, the device (100) comprising:
i) a multiplier device (110), configured to
receive a single-ended incoming signal (105), and
multiply the incoming signal (105) to provide a multiplied signal (115); and
ii) a divider device (120), configured to
receive the multiplied signal (115), and
divide the multiplied signal (115) to provide a differential signal (125a, 125b).
Further, a corresponding signal conversion method is described.-
公开(公告)号：US11849018B2
公开(公告)日：2023-12-19
申请号：US17662918
申请日：2022-05-11
Applicant: NXP B.V.
CPC classification number: H04L7/0337 , G06K7/10297 , H04L7/0033
Abstract: Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader. The card clock recovery system has: a phase lock loop having: a phase/frequency detector, which is configured to receive a reference signal provided at an RX port of a matching network during a receiving mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmission mode of the NFC transceiver, to receive a loop feedback signal, and to provide a phase error signal that represents a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal that is derived from the phase error signal, and to provide a filtered corrected phase error signal; a controllable oscillator, which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal, which is provided as the card clock generation control signal to a card clock generation unit of an NFC card transceiver, and as the loop feedback signal, via the loop feedback line, to the phase/frequency detector. The card clock recovery system further has a phase offset correction unit, which is configured to receive the phase error signal provided by the phase/frequency detector and to provide the corrected phase error signal to the loop filter, and which has a phase error sampling unit, a phase offset computation unit, and a phase subtractor unit.
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公开(公告)号：US20230246635A1
公开(公告)日：2023-08-03
申请号：US18061674
申请日：2022-12-05
Applicant: NXP B.V.
Inventor： Stefano Dal Toso , Olivier Susplugas
CPC classification number: H03K3/35613 , H03K5/2481
Abstract: It is described a signal converter device (100) for converting a single-ended signal to a differential signal, the device (100) comprising:
i) a multiplier device (110), configured to
receive a single-ended incoming signal (105), and
multiply the incoming signal (105) to provide a multiplied signal (115); and
ii) a divider device (120), configured to
receive the multiplied signal (115), and
divide the multiplied signal (115) to provide a differential signal (125a, 125b).
Further, a corresponding signal conversion method is described.
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