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    Latch circuit
    2.
    发明授权
    Latch circuit 有权
    锁存电路

    公开(公告)号：US09490782B2

    公开(公告)日：2016-11-08

    申请号：US14527865

    申请日：2014-10-30

    Applicant: NXP B.V.

    Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

    IPC: H03K3/3562 ,  H03K3/037 ,  H03K3/356 ,  H03K3/012

    CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/356104 ,  H03K3/356156

    Abstract: A latch circuit is based on a master-slave cross-coupled inverter pair configuration. The inverters of the slave circuit are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element. This circuit design avoids the need for an internal clock-buffer and enables single phase clocking, and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input and the output data signal is same.

    Abstract translation: 锁存电路基于主从交叉耦合逆变器对配置。 从电路的反相器耦合到高电压轨和低压轨，其中对于从电路逆变器对的两个反相器中的每一个，与一个电压轨的耦合通过电阻元件。 该电路设计避免了内部时钟缓冲器的需要，并且可以实现单相时钟，因此不需要内部时钟信号反相。 该电路可以实现低功耗，当输入和输出数据信号相同时，无冗余转换的动态功耗。

    MANAGING MEMORY IN AN ELECTRONIC DEVICE
    3.
    发明申请
    MANAGING MEMORY IN AN ELECTRONIC DEVICE 有权

    公开(公告)号：US20210081335A1

    公开(公告)日：2021-03-18

    申请号：US16996448

    申请日：2020-08-18

    Applicant: NXP B.V.

    Inventor： Alexandre Frey ,  Ralf Malzahn ,  Frank Ernst Johannes Siedel ,  Shameer Puthalan ,  Andreas Lessiak ,  Daniel Kershaw

    IPC: G06F12/14 ,  G06F12/02 ,  G06F12/0873 ,  G06F21/79

    Abstract: There is described a method of managing memory in an electronic device, the method comprising creating a set of equally sized logical regions in a logical address space, each logical region comprising a plurality of consecutive logical addresses, and mapping a subset of consecutive logical addresses within each logical region to a set of physical addresses within a corresponding physical memory region, the subset of consecutive logical addresses comprising the first logical address within the logical region, said first logical address being mapped to a base address within the corresponding physical memory region. Furthermore, there is described a controller for managing memory in an electronic device and a method of determining a physical memory address in a physical memory region using such a controller.

    TIMING CONTROL WITH BODY-BIAS
    5.
    发明申请
    TIMING CONTROL WITH BODY-BIAS 有权
    定时控制与身体偏差

    公开(公告)号：US20160098062A1

    公开(公告)日：2016-04-07

    申请号：US14504789

    申请日：2014-10-02

    Applicant: NXP B.V.

    Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

    IPC: G06F1/10

    CPC classification number: G06F1/10 ,  H03K5/159 ,  H03K19/094

    Abstract: Aspects of the present disclosure are directed to operating time-based circuitry. As may be implemented in connection with one or more embodiments, an apparatus and or method involved detecting timing characteristics of circuitry operating in respective clock domains, each having a semiconductor body region via which a clock signal path traverses. The respective semiconductor body regions are biased at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased.

    Abstract translation: 本公开的方面涉及操作基于时间的电路。 可以结合一个或多个实施例来实现，一种装置和/或方法涉及检测在相应时钟域中工作的电路的定时特性，每个时钟域具有时钟信号路径经过的半导体主体区域。 各个半导体本体区域以各自的偏置电平被偏置，这些偏置电平是基于检测到的偏移半导体主体区域的时钟信号路径的定时特性。

    LATCH CIRCUIT
    6.
    发明申请
    LATCH CIRCUIT 有权
    锁定电路

    公开(公告)号：US20150123722A1

    公开(公告)日：2015-05-07

    申请号：US14527865

    申请日：2014-10-30

    Applicant: NXP B.V.

    Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

    IPC: H03K3/3562 ,  H03K3/012

    CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/356104 ,  H03K3/356156

    Abstract: A latch circuit is based on a master-slave cross-coupled inverter pair configuration. The inverters of the slave circuit are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element. This circuit design avoids the need for an internal clock-buffer and enables single phase clocking, and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input and the output data signal is same.

    Abstract translation: 锁存电路基于主从交叉耦合逆变器对配置。 从电路的反相器耦合到高电压轨和低压轨，其中对于从电路逆变器对的两个反相器中的每一个，与一个电压轨的耦合通过电阻元件。 该电路设计避免了内部时钟缓冲器的需要，并且可以实现单相时钟，因此不需要内部时钟信号反相。 该电路可以实现低功耗，当输入和输出数据信号相同时，无冗余转换的动态功耗。

    Stacked clock distribution for low power devices
    7.
    发明授权
    Stacked clock distribution for low power devices 有权
    低功耗器件的堆叠时钟分配

    公开(公告)号：US08947149B1

    公开(公告)日：2015-02-03

    申请号：US14136137

    申请日：2013-12-20

    Applicant: NXP B.V.

    Inventor： Ajay Kapoor ,  Ralf Malzahn ,  Rinze Ida Mechtildis Peter Meijer ,  Peter Thueringer

    IPC: G06F1/04 ,  H03K3/012

    CPC classification number: H03K5/003 ,  G06F1/10

    Abstract: Embodiments of a clock distribution device and a method of clock distribution are described. In one embodiment, a clock distribution device includes a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges and a load circuit. The stacked clock driver circuit includes stacked driver circuits configured to generate output clock signals that swing between the different voltage ranges. The load circuit includes load networks of different semiconductor types. Each of the load networks are configured to be driven by one of the output clock signals. Other embodiments are also described.

    Abstract translation: 时钟分配装置的实施例和时钟分配方法被描述。 在一个实施例中，时钟分配装置包括堆叠的时钟驱动器电路，其被配置为对在不同电压范围之间摆动的输入时钟信号和负载电路执行时钟信号电荷循环。 堆叠式时钟驱动器电路包括被配置为产生在不同电压范围之间摆动的输出时钟信号的堆叠驱动器电路。 负载电路包括不同半导体类型的负载网络。 每个负载网络被配置为由其中一个输出时钟信号驱动。 还描述了其它实施例。

    Fault resistant flip-flop
    8.
    发明授权
    Fault resistant flip-flop 有权
    防故障触发器

    公开(公告)号：US09590598B2

    公开(公告)日：2017-03-07

    申请号：US14863369

    申请日：2015-09-23

    Applicant: NXP B.V.

    Inventor： Vibhu Sharma ,  Ralf Malzahn

    IPC: H03K3/037 ,  H03K3/3562 ,  H03K3/011

    CPC classification number: H03K3/0372 ,  H03K3/011 ,  H03K3/0375 ,  H03K3/35625

    Abstract: A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic gates (21, 22, 31, 32). A cross coupling connection of the slave or master latch (30, 20) comprises a resistive element (8, 9, 11, 12) arranged to reduce the sensitivity of the flip-flop (10) to a current injection.

    Abstract translation: 公开了一种触发器（10），包括从锁存器（30）和主锁存器（20）。 从机和主机锁存器中的每一个包括一对交叉耦合的逻辑门（21,22,31,32）。 从属或主锁存器（30,20）的交叉耦合连接包括布置成将触发器（10）的灵敏度降低到电流注入的电阻元件（8,9,11,12）。

    Timing control with body-bias
    9.
    发明授权
    Timing control with body-bias 有权
    具有身体偏倚的时机控制

    公开(公告)号：US09417657B2

    公开(公告)日：2016-08-16

    申请号：US14504789

    申请日：2014-10-02

    Applicant: NXP B.V.

    Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

    IPC: H03K3/00 ,  G06F1/10 ,  H03K5/159 ,  H03K19/094

    CPC classification number: G06F1/10 ,  H03K5/159 ,  H03K19/094

    Abstract: Aspects of the present disclosure are directed to operating time-based circuitry. As may be implemented in connection with one or more embodiments, an apparatus and or method involved detecting timing characteristics of circuitry operating in respective clock domains, each having a semiconductor body region via which a clock signal path traverses. The respective semiconductor body regions are biased at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased.

    Abstract translation: 本公开的方面涉及操作基于时间的电路。 可以结合一个或多个实施例来实现，一种装置和/或方法涉及检测在相应时钟域中工作的电路的定时特性，每个时钟域具有时钟信号路径经过的半导体主体区域。 各个半导体本体区域以各自的偏置电平被偏置，这些偏置电平是基于检测到的偏移半导体主体区域的时钟信号路径的定时特性。

    FAULT RESISTANT FLIP-FLOP
    10.
    发明申请
    FAULT RESISTANT FLIP-FLOP 有权
    防止飞溅

    公开(公告)号：US20160087611A1

    公开(公告)日：2016-03-24

    申请号：US14863369

    申请日：2015-09-23

    Applicant: NXP B.V.

    Inventor： Vibhu Sharma ,  Ralf Malzahn

    IPC: H03K3/037 ,  H03K3/011 ,  H03K3/3562

    CPC classification number: H03K3/0372 ,  H03K3/011 ,  H03K3/0375 ,  H03K3/35625

    Abstract: A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic gates (21, 22, 31, 32). A cross coupling connection of the slave or master latch (30, 20) comprises a resistive element (8, 9, 11, 12) arranged to reduce the sensitivity of the flip-flop (10) to a current injection.

    Abstract translation: 公开了一种触发器（10），包括从锁存器（30）和主锁存器（20）。 从机和主机锁存器中的每一个包括一对交叉耦合的逻辑门（21,22,31,32）。 从属或主锁存器（30,20）的交叉耦合连接包括布置成将触发器（10）的灵敏度降低到电流注入的电阻元件（8,9,11,12）。

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