公开(公告)号：US20230126891A1

公开(公告)日：2023-04-27

申请号：US17512231

申请日：2021-10-27

Applicant: NXP B.V.

Inventor： Ravichandar Reddy Geetla ,  Deependra Kumar Jain ,  Gaurav Agrawal ,  Ravi Kumar

IPC: H03L7/099 ,  H03L7/081 ,  H03L7/197 ,  H03M3/00

Abstract: An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

公开(公告)号：US11784651B2

公开(公告)日：2023-10-10

申请号：US17512231

申请日：2021-10-27

Applicant: NXP B.V.

Inventor： Ravichandar Reddy Geetla ,  Deependra Kumar Jain ,  Gaurav Agrawal ,  Ravi Kumar

IPC: H03L7/099 ,  H03L7/081 ,  H03L7/197 ,  H03M3/00

CPC classification number: H03L7/0992 ,  H03L7/0814 ,  H03L7/0995 ,  H03L7/1974 ,  H03M3/30

Abstract: An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.