公开(公告)号：US20180164420A1

公开(公告)日：2018-06-14

申请号：US15835186

申请日：2017-12-07

Applicant: NXP B.V.

Inventor： Yu LIN ,  Erwin JANSSEN ,  Konstantinos DORIS ,  Vladislav DYACHENKO ,  Athon ZANIKOPOULOS

IPC: G01S13/34 ,  G01R23/04

CPC classification number: G01S13/341 ,  G01R23/04 ,  G01S13/342 ,  G06F1/022 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1466 ,  H03J3/04

Abstract: A frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal. The frequency estimation signal generator component comprises a counter component arranged to sequentially output a sequence of control signal patterns over a plurality of digital control signals under the control of an oscillating signal derived from the received input frequency signal terns. The frequency estimation signal generator further comprises a continuous waveform generator component arranged to receive the plurality of digital control signals and a weighted analogue signal for each of the received digital control signals, and to output a continuous waveform signal comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state. The frequency conversion component is arranged to derive the frequency estimation signal from the continuous waveform signal output by the continuous waveform generator component

公开(公告)号：US20200169166A1

公开(公告)日：2020-05-28

申请号：US16201088

申请日：2018-11-27

Applicant: NXP B.V.

Inventor： Vladislav DYACHENKO ,  Nenad PAVLOVIC

IPC: H02M3/07 ,  H03L7/089

Abstract: Embodiments of a method for operating a charge pump and a charge pump are disclosed. In an embodiment, a method for operating a charge pump involves during a first operating phase of the charge pump, setting a first current source of the charge pump according to a second current source of the charge pump, and, during a second operating phase of the charge pump that is subsequent to the first operating phase, providing current from the first current source to a load of the charge pump.

公开(公告)号：US20160241301A1

公开(公告)日：2016-08-18

申请号：US15041217

申请日：2016-02-11

Applicant: NXP B.V.

Inventor： NENAD PAVLOVIC ,  Vladislav DYACHENKO ,  Tarik SARIC

IPC: H04B1/7073

CPC classification number: H04B1/7073 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0991 ,  H03L7/1976 ,  H04B2001/6912 ,  H04B2201/7073

Abstract: A phase locked loop is disclosed having a frequency controlled oscillator (42), a feedback path, a time to digital converter (10) and a memory. The frequency controlled oscillator (42) comprises a first control input (135, 136) for varying the frequency of the output (106) of the frequency controlled oscillator (42) so as to track a reference frequency (101) and a second control input (139) for modulating the frequency of the output signal (106) so as to produce a chirp. The feedback path is configured to provide an input signal (107) to the time to digital converter (10), and comprises modulation cancelling module (14) operable to remove the frequency modulation resulting from the second control input (139) from the output signal (106). The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input (139). The phase locked loop is operable in a chirp mode, in which the second control input (139) is produced by determining a value for the second control input (139) corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input (135, 136) based on the feedback path from which the modulation cancelling module (14) has removed the frequency modulation resulting from the second control input (139).

Abstract translation: 公开了一种具有频率控制振荡器（42），反馈路径，时间到数字转换器（10）和存储器的锁相环。 频率控制振荡器（42）包括用于改变频率控制振荡器（42）的输出（106）的频率的第一控制输入（135,136），以便跟踪参考频率（101）和第二控制输入 （139），用于调制输出信号（106）的频率，以便产生啁啾声。 反馈路径被配置为向数字转换器（10）提供输入信号（107），并且包括调制解除模块（14），其可操作以从输出信号中去除由第二控制输入（139）产生的频率调制 （106）。 存储器存储每个对应于期望啁啾频率并且补偿频率控制振荡器对第二控制输入（139）的响应中的非线性的第二控制输入值。 锁相环可以在啁啾模式下操作，其中通过基于所存储的第二控制输入值确定对应于期望啁啾频率的第二控制输入（139）的值来产生第二控制输入（139） 存储器，并且其中所述锁相环被配置为基于所述调制解除模块（14）从其中移除了由所述第二控制输入（139）产生的频率调制的反馈路径来确定所述第一控制输入（135,136） 。