公开(公告)号：US20240020186A1

公开(公告)日：2024-01-18

申请号：US18348403

申请日：2023-07-07

Applicant: NXP B.V.

Inventor： Xiankun Jin ,  Andres Barrilado Gonzalez ,  Mathieu Blazy-Winning

IPC: G06F11/00 ,  G06F11/32

CPC classification number: G06F11/008 ,  G06F11/324

Abstract: A layered architecture for managing health of the electronic system comprises a plurality of health subsystems. Health subsystems receive health information from health monitors coupled to respective components of the electronic system and provide the health information to another health subsystem. Based on the received health information, the other health subsystem uses predictive data analytics to determine a health condition of the electronic system and update a health policy based on the predictive data analytics to improve prediction of the health condition of the electronic system.

公开(公告)号：US11489535B1

公开(公告)日：2022-11-01

申请号：US17302729

申请日：2021-05-11

Applicant: NXP B.V.

Inventor： Xiankun Jin ,  Douglas Alan Garrity ,  Mark Lehmann ,  Kumar Abhishek

IPC: H03M1/10

Abstract: Body text indent—does not have paragraph numbering turned on. Not needed in the Abstract. An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.

公开(公告)号：US11418188B1

公开(公告)日：2022-08-16

申请号：US17317592

申请日：2021-05-11

Applicant: NXP B.V.

Inventor： Kushagra Bhatheja ,  Chris C. Dao ,  Xiankun Jin

IPC: H03K17/687 ,  H03M1/12 ,  H03K19/20 ,  H03K5/00

Abstract: In an integrated circuit, a bootstrapped switch includes a capacitor and first, second, and third transistors. The first transistor has a first current electrode coupled to a first voltage supply node and a gate electrode coupled to a first circuit node. The second transistor has a first current electrode coupled to a second voltage supply terminal, a second current electrode coupled to a top terminal of the capacitor, and a control electrode coupled to the first circuit node. The third transistor has a first current electrode coupled to the first voltage supply terminal, a control electrode coupled to the first circuit node, and a second current electrode coupled to a body terminal of the second transistor. The fourth transistor has a first current electrode coupled to the body terminal of the second transistor, and a second current electrode coupled to the top terminal of the capacitor.

公开(公告)号：US20200072900A1

公开(公告)日：2020-03-05

申请号：US16117317

申请日：2018-08-30

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Xiankun Jin ,  Tao Chen

IPC: G01R31/3163 ,  H03M1/10 ,  G01R35/00

Abstract: An example analog-test-bus (ATB) apparatus includes a plurality of comparator circuits, each having an output port, and a pair of input ports of opposing polarity including an inverting port and a non-inverting port, a plurality of circuit nodes to be selectively connected to the input ports of a first polarity, and at least one digital-to-analog converter (DAC) to drive the input ports of the plurality of comparator circuits. The apparatus further includes data storage and logic circuitry that accounts for inaccuracies attributable to the plurality of comparator circuits by providing, for each comparator circuit, a set of calibration data indicative of the inaccuracies for adjusting comparison operations performed by the plurality of comparator circuits.

公开(公告)号：US20220368338A1

公开(公告)日：2022-11-17

申请号：US17302729

申请日：2021-05-11

Applicant: NXP B.V.

Inventor： Xiankun Jin ,  Douglas Alan Garrity ,  Mark Lehmann ,  Kumar Abhishek

IPC: H03M1/10

Abstract: An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.