公开(公告)号：US10032904B2

公开(公告)日：2018-07-24

申请号：US15378458

申请日：2016-12-14

申请人： NXP USA, Inc.

发明人： Patrice M. Parris ,  Hubert M. Bode ,  Weize Chen ,  Richard J. DeSouza ,  Andreas Laudenbach ,  Kurt U. Neugebauer

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/36

摘要： A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

公开(公告)号：US20170146485A1

公开(公告)日：2017-05-25

申请号：US15427846

申请日：2017-02-08

申请人： NXP USA, Inc.

发明人： Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza ,  Md M. Hoque ,  John M. McKenna

IPC分类号： G01N27/414 ,  G11C16/04 ,  H01L21/28 ,  G05F1/575 ,  H01L29/788 ,  H01L49/02

CPC分类号： G01N27/4148 ,  G05F1/575 ,  G11C16/0416 ,  H01L21/28035 ,  H01L23/5223 ,  H01L27/11526 ,  H01L27/11558 ,  H01L28/40 ,  H01L28/60 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

公开(公告)号：US20170092760A1

公开(公告)日：2017-03-30

申请号：US15378458

申请日：2016-12-14

申请人： NXP USA, Inc.

发明人： Patrice M. Parris ,  Hubert M. Bode ,  Weize Chen ,  Richard J. DeSouza ,  Andreas Laudenbach ,  Kurt U. Neugebauer

IPC分类号： H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/7823 ,  H01L21/761 ,  H01L27/0255 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

公开(公告)号：US09964516B2

公开(公告)日：2018-05-08

申请号：US15427846

申请日：2017-02-08

申请人： NXP USA, Inc.

发明人： Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza ,  Md M. Hoque ,  John M. McKenna

IPC分类号： G11C16/04 ,  G01N27/414 ,  H01L29/788 ,  H01L49/02 ,  H01L21/28 ,  G05F1/575

CPC分类号： G01N27/4148 ,  G05F1/575 ,  G11C16/0416 ,  H01L21/28035 ,  H01L23/5223 ,  H01L27/11526 ,  H01L27/11558 ,  H01L28/40 ,  H01L28/60 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.