公开(公告)号：US5692153A

公开(公告)日：1997-11-25

申请号：US405058

申请日：1995-03-16

申请人： Nadeem Malik ,  Brian O'Krafka ,  Avijit Saha ,  Shahram Salamian

发明人： Nadeem Malik ,  Brian O'Krafka ,  Avijit Saha ,  Shahram Salamian

IPC分类号： G06F15/16 ,  G06F11/28 ,  G06F12/08 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F12/0806 ,  G06F11/28

摘要： A method and system are disclosed for verifying consistency of an instruction execution order of a multiprocessor data processing system with a specified memory consistency model. Each processor within the multiprocessor data processing system executes instructions from an associated one of a number of instruction streams, which include instructions that store a number of unique values from multiple processors to a single selected address within memory. One of the unique values is loaded from the selected address to a particular processor within the data processing system. A set of valid values which may be returned by the loading step is determined according to the specified memory consistency model. By comparing the unique value with members of the set of valid values, the instruction execution order of the multiprocessor data processing system is verified. Utilizing the unique value which was returned by the load instruction, the set of valid values may then be updated.

摘要翻译： 公开了一种用于验证多处理器数据处理系统的指令执行顺序与指定的存储器一致性模型的一致性的方法和系统。 多处理器数据处理系统中的每个处理器从多个指令流中的相关联的一个指令流中执行指令，指令流包括将多个处理器的唯一值存储到存储器内的单个选定地址的指令。 唯一值中的一个从所选地址加载到数据处理系统中的特定处理器。 根据指定的内存一致性模型确定可由加载步骤返回的一组有效值。 通过将唯一值与有效值集合的成员进行比较，验证多处理器数据处理系统的指令执行顺序。 利用加载指令返回的唯一值，然后可以更新该组有效值。

公开(公告)号：US5606666A

公开(公告)日：1997-02-25

申请号：US277394

申请日：1994-07-19

申请人： Carl H. Grant ,  Jace W. Krull ,  Charles E. Kuhlmann ,  Shahram Salamian ,  Eugene M. Thomas ,  James T. Tsevdos

发明人： Carl H. Grant ,  Jace W. Krull ,  Charles E. Kuhlmann ,  Shahram Salamian ,  Eugene M. Thomas ,  James T. Tsevdos

IPC分类号： G06F15/16 ,  G06F13/00 ,  G06F15/17 ,  G06F15/177 ,  H04L29/06 ,  H04L29/08

CPC分类号： G06F15/17 ,  H04L29/06 ,  H04L69/32

摘要： A computer system is provided in which asynchronously operating processing elements in the system are connected by means of an interconnection media so as to permit communication between an executing program on one of the processing elements with the memory on another processing element. Inter-processing communication logic located on each of the processing elements permits communication between executing programs on any one processing element. Inter-delivery support hardware is provided for interfacing between the interconnection media and the inter-processing communication logic. The inter-delivery support hardware operates asynchronously with respect to the executing programs on the processing elements for (i) enqueuing control elements obtained by a function on a first processing element from physical memory on the first processing element; (ii) temporarily storing the enqueued control elements in a first memory device associated with the first processing element; (iii) copying over the interconnection media via a copy transaction the temporarily stored control elements from the first memory device to a second memory device associated with a second processing element; and (iv) dequeuing the copied control elements from the second memory device to physical memory on the second processing element.

摘要翻译： 提供了一种计算机系统，其中系统中的异步操作处理元件通过互连介质连接，以便允许处理元件之一上的执行程序与另一个处理元件上的存储器之间进行通信。 位于每个处理元件上的处理间通信逻辑允许在任何一个处理元件上执行程序之间的通信。 交互支持硬件被提供用于在互连介质和处理间通信逻辑之间进行接口。 交付支持硬件相对于处理元件上的执行程序异步地操作，用于（i）通过第一处理元件上的物理存储器对通过第一处理元件的功能获得的控制元素进行排队; （ii）将入队控制元件临时存储在与第一处理元件相关联的第一存储器件中; （iii）通过复制事务将临时存储的控制元件从第一存储器设备复制到互连介质到与第二处理元件相关联的第二存储器设备; 以及（iv）将复制的控制元件从第二存储器装置出发到第二处理元件上的物理存储器。

公开(公告)号：US5740353A

公开(公告)日：1998-04-14

申请号：US572472

申请日：1995-12-14

申请人： Jeffrey Thomas Kreulen ,  Sriram Srinivasan Mandyam ,  Brian Walter O'Krafka ,  Shahram Salamian ,  Ramanathan Raghavan

发明人： Jeffrey Thomas Kreulen ,  Sriram Srinivasan Mandyam ,  Brian Walter O'Krafka ,  Shahram Salamian ,  Ramanathan Raghavan

IPC分类号： G06F11/263 ,  G06F11/00

CPC分类号： G06F11/263 ,  G06F12/0815 ,  G06F2212/1032

摘要： A method and apparatus for creating a multiprocessor verification environment. A Multiprocessor Test Generator (MPTG) generates a set of test cases in a Multiprocessor Test Language (MTL) format subject to constraints and enumeration controls in a test specification. An abstract system model of the machine under test is inputted to the Multiprocessor Test Generator. The Multiprocessor Test Generator (MPTG) receives the test specification and abstract system model, accesses a system specific database and generates test cases based on the constraints in the test specification in a Multiprocessor Test Language (MTL). The Multiprocessor Test Language (MTL) test cases are inputted to a Multiprocessor Test Executive (MPX) which controls the issuance of the test cases to a cache-coherent multiprocessor system, and monitors their completion in order to verify operation of the cache-coherent multiprocessor system.

摘要翻译： 一种用于创建多处理器验证环境的方法和装置。 多处理器测试生成器（MPTG）会根据测试规范中的约束和枚举控制，以多处理器测试语言（MTL）格式生成一组测试用例。 被测机器的抽象系统模型被输入到多处理器测试发生器。 多处理器测试生成器（MPTG）接收测试规范和抽象系统模型，访问系统特定的数据库，并根据多处理器测试语言（MTL）中的测试规范中的约束生成测试用例。 多处理器测试语言（MTL）测试用例被输入到多处理器测试执行程序（MPX），该处理器测试执行程序控制测试用例发布到高速缓存一致的多处理器系统，并监视其完成以验证高速缓存相关多处理器的操作 系统。

公开(公告)号：US5452470A

公开(公告)日：1995-09-19

申请号：US294292

申请日：1994-08-23

申请人： Robert F. Kantner, Jr. ,  Tze-Wing Keung ,  Jace W. Krull ,  Shahram Salamian

发明人： Robert F. Kantner, Jr. ,  Tze-Wing Keung ,  Jace W. Krull ,  Shahram Salamian

IPC分类号： G06F13/00 ,  G09G5/39 ,  G09G5/393 ,  G06F12/00

CPC分类号： G09G5/39 ,  G09G2360/126 ,  G09G5/393

摘要： A data communication system contains a dual-port/dual-access-mode storage subsystem, and a communication controller connecting between that subsystem and external data communication channels. The storage subsystem includes one or more dual-port/dual-access mode storage devices consisting of a pair of random access and sequential access memory arrays, with a parallel block transfer connection between the arrays. The sequential access array can store a large block of up to N bytes (N for example equal to 256), and the random access array can store multiple such blocks. The subsystem also has RAM and SAM access ports respectively controllable in random access and sequential access modes and respectively connecting to the random access and sequential access arrays. In random access mode a group of from 1 to 4 bytes is transferred between the controller and a specified address in the random access array, and in sequential access mode a block of up to N bytes is transferred in a sequential manner between the controller and the sequential access array and in a parallel manner between that array and a discretely addressed block of space in the random access array. Transfers of relatively long and short data communication messages are routed respectively through the SAM and RAM external ports by the controller, so as to efficiently match bandwidth requirements of external communication channels with access characteristics of the RAM and SAM ports.

摘要翻译： 数据通信系统包含双端口/双访问模式存储子系统，以及连接在该子系统与外部数据通信通道之间的通信控制器。 存储子系统包括一个或多个双端口/双访问模式存储设备，其由一对随机访问和顺序访问存储器阵列组成，在阵列之间具有并行块传输连接。 顺序访问阵列可以存储多达N个字节（N例如等于256）的大块，并且随机存取阵列可以存储多个这样的块。 该子系统还具有分别在随机接入和顺序接入模式中可控的RAM和SAM接入端口，分别连接到随机接入和顺序接入阵列。 在随机存取模式中，在控制器和随机存取阵列中的指定地址之间传送1至4字节的组，并且在顺序存取模式中，以控制器和控制器之间的顺序方式传送多达N个字节的块 顺序访问阵列并且以并行方式在该阵列和随机存取阵列中离散地寻址的空间块之间。 通过控制器分别通过SAM和RAM外部端口路由相对较长和短的数据通信消息的传输，从而高效地匹配外部通信信道的带宽要求与RAM和SAM端口的访问特性。