公开(公告)号：US06657249B2

公开(公告)日：2003-12-02

申请号：US10189575

申请日：2002-07-08

申请人： Naho Nishioka ,  Naoki Tsuji

发明人： Naho Nishioka ,  Naoki Tsuji

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A nonvolatile semiconductor memory device capable of readily distinctively forming transistors in a peripheral circuit part and a transistor in a memory cell part while minimizing the number of times of high-temperature heat treatment are obtained. In the peripheral circuit part, at least one of a first transistor and a second transistor has a lower conductive layer having the same perpendicular structure as a floating gate, an intermediate insulator film including an insulator film of the same perpendicular structure as an inter-gate isolation film and an upper conductive layer of the same perpendicular structure as a conductive layer of a control gate in ascending order on a gate insulator film thereof, and the intermediate insulator film includes a conduction part electrically connecting the upper conductive layer and the lower conductive layer with each other.

摘要翻译： 获得能够在最小化高温热处理次数的同时，在外围电路部分中容易地形成晶体管和存储单元部分中的晶体管的非易失性半导体存储器件。 在外围电路部分中，第一晶体管和第二晶体管中的至少一个具有与浮置栅极具有相同垂直结构的下导电层，包括与栅极相同垂直结构的绝缘膜的中间绝缘膜 隔离膜和与导电层相同的垂直结构的上导电层，其栅极绝缘膜上以升序排列，并且中间绝缘膜包括将上导电层和下导电层电连接的导电部分 与彼此。

公开(公告)号：US5994733A

公开(公告)日：1999-11-30

申请号：US3641

申请日：1998-01-07

申请人： Naho Nishioka ,  Natsuo Ajika ,  Hiroshi Onoda

发明人： Naho Nishioka ,  Natsuo Ajika ,  Hiroshi Onoda

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546

摘要： Each nonvolatile transistor comprises a floating gate electrode, an ONO film and a control gate electrode. An upper surface of a silicon oxide film is positioned at a height between upper and lower surfaces of the floating gate electrode. The control gate electrode continuously extends on the floating gate electrode and the silicon oxide film in a prescribed arrangement direction.

摘要翻译： 每个非易失性晶体管包括浮栅电极，ONO膜和控制栅电极。 氧化硅膜的上表面位于浮栅电极的上表面和下表面之间的高度处。 控制栅电极在规定的布置方向上在浮栅和氧化硅膜上连续地延伸。

公开(公告)号：US06410452B1

公开(公告)日：2002-06-25

申请号：US09795309

申请日：2001-03-01

申请人： Naho Nishioka

发明人： Naho Nishioka

IPC分类号： H01L21302

摘要： A method of manufacturing a semiconductor device having a trench isolation structure includes patterning a mask film on a semiconductor substrate, forming a trench by etching the semiconductor substrate by use of the mask film, filling the trench with an insulating film by repeating depositing the insulating film in the trench and etching the insulating film by sputter etching, removing the mask film, and removing the insulating film by etching a predetermined amount of the insulating film filled in the trench. According to the sputter etching in the step of filling the trench with the insulating film, an edge between a surface of the substrate and an inner wall surface of the trench forms an inclined surface to the surface of the substrate.

公开(公告)号：US06784057B2

公开(公告)日：2004-08-31

申请号：US09920951

申请日：2001-08-03

申请人： Naho Nishioka

发明人： Naho Nishioka

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A semiconductor device of which the process is simplified so that the manufacturing cost can be reduced and, at the same time, which has a semiconductor element that can control a current of high voltage is provided. The semiconductor device includes first and second semiconductor elements and the first semiconductor element includes a lower electrode formed above a substrate, an intermediate insulating film formed on the lower electrode and an upper electrode formed on the insulating film. The second semiconductor element includes a gate insulating film, which is formed on the substrate and which includes the same layer as that of the intermediate insulating film, and a gate electrode formed on the gate insulating film.

摘要翻译： 其工艺简化的半导体器件能够降低制造成本，并且同时具有能够控制高电压电流的半导体元件。 半导体器件包括第一和第二半导体元件，并且第一半导体元件包括形成在衬底上的下电极，形成在下电极上的中间绝缘膜和形成在绝缘膜上的上电极。 第二半导体元件包括形成在基板上并且包括与中间绝缘膜相同的层的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。

公开(公告)号：US06756630B2

公开(公告)日：2004-06-29

申请号：US10096487

申请日：2002-03-13

申请人： Naho Nishioka

发明人： Naho Nishioka

IPC分类号： H01L29788

CPC分类号： H01L27/112 ,  H01L21/76802 ,  H01L21/823871 ,  H01L27/105 ,  H01L27/11546

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a main surface and a plurality of transistors formed on the main surface. The transistors each include a gate electrode, a diffusion layer formed adjacent to the gate electrode and contacts communicating with the diffusion layer. The contacts corresponding to the transistors include a contact having a first distance from the gate electrode and a contact having a second distance from the gate electrode that is longer than the first distance.

摘要翻译： 非易失性半导体存储器件包括具有主表面的半导体衬底和形成在主表面上的多个晶体管。 晶体管各自包括栅电极，邻近栅电极形成的扩散层和与扩散层连通的触点。 对应于晶体管的触点包括具有距离栅电极的第一距离的触点和距离栅电极具有比第一距离长的第二距离的触点。