公开(公告)号：US07193265B2

公开(公告)日：2007-03-20

申请号：US10907006

申请日：2005-03-16

申请人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

发明人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

IPC分类号： H01L29/788

CPC分类号： G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883

摘要： The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and a second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a N+ doped region. The floating gate overlaps with the N-well and extends to the N+ doped region. The overlapped region of the P-well and the N+ doped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

摘要翻译： 单多晶硅EEPROM包括串联连接到第二PMOS晶体管的第一PMOS晶体管。 第一和第二PMOS晶体管都形成在P型衬底的N阱上。 第一PMOS晶体管包括浮置栅极，第一P + +掺杂漏极区域和第一P + +掺杂源极区域。 第二PMOS晶体管包括栅极和第二P + +掺杂源极区域。 第一PMOS晶体管的第一P + SUP掺杂漏区用作第二PMOS晶体管的漏极。 二极管位于包括P阱和N + +掺杂区的P型衬底中。 浮栅与N阱重叠并延伸到N + +掺杂区。 浮置栅极下面的P阱和N + + / / P>掺杂区域结的重叠区域用作第一PMOS晶体管附近的雪崩注入点。

公开(公告)号：US20060208306A1

公开(公告)日：2006-09-21

申请号：US10907006

申请日：2005-03-16

申请人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

发明人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

IPC分类号： H01L29/788

CPC分类号： G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883

摘要： The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and a second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a N+ doped region. The floating gate overlaps with the N-well and extends to the N+ doped region. The overlapped region of the P-well and the N+ doped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

摘要翻译： 单多晶硅EEPROM包括串联连接到第二PMOS晶体管的第一PMOS晶体管。 第一和第二PMOS晶体管都形成在P型衬底的N阱上。 第一PMOS晶体管包括浮置栅极，第一P + +掺杂漏极区域和第一P + +掺杂源极区域。 第二PMOS晶体管包括栅极和第二P + +掺杂源极区域。 第一PMOS晶体管的第一P + SUP掺杂漏区用作第二PMOS晶体管的漏极。 二极管位于包括P阱和N + +掺杂区的P型衬底中。 浮栅与N阱重叠并延伸到N + +掺杂区。 浮置栅极下面的P阱和N + + / / P>掺杂区域结的重叠区域用作第一PMOS晶体管附近的雪崩注入点。

公开(公告)号：US06440803B1

公开(公告)日：2002-08-27

申请号：US10047685

申请日：2002-01-14

申请人： Shui-Chin Huang ,  Yen-hung Yeh ,  Tso-Hung Fan ,  Chun-Yi Yang ,  Chun-Jung Lin

发明人： Shui-Chin Huang ,  Yen-hung Yeh ,  Tso-Hung Fan ,  Chun-Yi Yang ,  Chun-Jung Lin

IPC分类号： H01L218238

CPC分类号： H01L27/11266 ,  H01L27/112

摘要： A method of fabricating a mask ROM, in which conductive strips are formed with a cap layer on each of them, then a plurality of spacers are formed on the side-walls of the conductive strips, while the substrate under the spacers are used as the coding regions. The buried bit-lines are formed in the substrate between the spacers, then a two-step coding process is performed, wherein the coding regions at the first and the second side of the conductive strips are selectively doped by a first and a second tilt coding implantation with a first and a second coding mask. After the second mask layer and the cap layer are removed, a conductive layer is formed over the substrate, then the conductive layer and the conductive strips are patterned successively to form a plurality of word-lines and plural gates, respectively.

摘要翻译： 一种制造掩模ROM的方法，其中在每个掩模ROM上形成具有覆盖层的导电条，然后在导电条的侧壁上形成多个间隔物，同时使用间隔物下的基板作为 编码区域。 掩埋位线形成在间隔物之间​​的衬底中，然后进行两步编码处理，其中导电条的第一和第二侧的编码区被第一和第二倾斜编码 用第一和第二编码掩模进行植入。 在除去第二掩模层和盖层之后，在衬底上形成导电层，然后分别对导电层和导电条进行图案化以形成多个字线和多个栅极。

公开(公告)号：US06380042B1

公开(公告)日：2002-04-30

申请号：US09876732

申请日：2001-06-07

申请人： Shui-Chin Huang

发明人： Shui-Chin Huang

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/115 ,  H01L27/11521

摘要： A self-aligned contact process is provided on a semiconductor substrate having at least two gate structures and a plurality of lightly ion-doped regions on the semiconductor substrate. Each of the gate structures has a gate layer and a cap layer formed on the gate layer. A first sidewall spacer is formed on the sidewalls of the gate structure, and then a heavy ion-doped region is formed on the exposed lightly ion-doped region. Next, a first dielectric layer is formed to fill the gap between adjacent first sidewall spacers. Part of the first sidewall spacer and part of the first dielectric layer is removed to expose the cap layer. A second spacer is then formed on the exposed sidewall of the cap layer. Next, a second dielectric layer is formed to fill the gap between adjacent second sidewall spacers. Finally, the second dielectric layer and the first dielectric layer positioned adjacent gate structures are removed to expose the second ion-doped region so as to form a contact hole.

摘要翻译： 在半导体衬底上具有至少两个栅极结构和半导体衬底上的多个轻离子掺杂区域的自对准接触工艺。 每个栅极结构具有形成在栅极层上的栅极层和盖层。 在栅极结构的侧壁上形成第一侧壁间隔物，然后在暴露的轻微离子掺杂区域上形成重离子掺杂区域。 接下来，形成第一电介质层以填充相邻的第一侧壁间隔件之间的间隙。 第一侧壁间隔件的一部分和第一介电层的一部分被去除以暴露盖层。 然后在盖层的暴露的侧壁上形成第二间隔物。 接下来，形成第二电介质层以填充相邻的第二侧壁间隔件之间的间隙。 最后，去除位于栅极结构附近的第二电介质层和第一电介质层，以露出第二离子掺杂区域以形成接触孔。

公开(公告)号：US06645816B2

公开(公告)日：2003-11-11

申请号：US10050082

申请日：2002-01-15

申请人： Shui-Chin Huang

发明人： Shui-Chin Huang

IPC分类号： H01L218246

CPC分类号： H01L27/1122 ,  H01L27/112 ,  H01L27/1126

摘要： A method of fabricating a memory device having a buried source/drain region is provided, in which a dielectric layer and a word-line is sequentially formed on the substrate, then a buried source/drain region is formed in the substrate. After that, a barrier layer is formed on the exposed surface of the word-line, then a metal layer is formed over the substrate. The metal layer is patterned to leave a portion covering the buried source/drain region beside the word-line and crossing over the word-line.

摘要翻译： 提供一种制造具有掩埋源极/漏极区域的存储器件的方法，其中介电层和字线顺序地形成在衬底上，然后在衬底中形成掩埋的源极/漏极区域。 之后，在字线的暴露表面上形成阻挡层，然后在衬底上形成金属层。 金属层被图案化以留下在字线旁边覆盖掩埋源极/漏极区的部分并跨越字线。

公开(公告)号：US06589842B2

公开(公告)日：2003-07-08

申请号：US09855129

申请日：2001-05-14

申请人： Shui-Chin Huang

发明人： Shui-Chin Huang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： The present invention relates to discloses a manufacturing method of a gate-split flash memory, which is suitable for a self-align contact process and fully-salicide-compatible process. The present invention masks the invalid peaks with a thick passivation layer to obtain the purpose of removing the invalid peaks in the manufacturing process of a gate-split flash memory. The present invention deposits a nitride spacer to define a pattern of a floating gate of the flash memory, so that a channel length of the floating gate can be finely defined. The present invention also utilizes a mask pattern to define the floating gate region of the flash memory, and the manufacturing process will be smooth and cheap.

公开(公告)号：US07054196B2

公开(公告)日：2006-05-30

申请号：US10728137

申请日：2003-12-03

申请人： Chien-Hung Chen ,  Shui-Chin Huang

发明人： Chien-Hung Chen ,  Shui-Chin Huang

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0433 ,  H01L27/115

摘要： A method for programming a P-channel EEPROM having an N-well, a floating gate, a control gate, a P-type source region and a P-type drain region is provided. In the method, the N-well is grounded, a first positive voltage is applied to the control gate, a second positive voltage or a programming current is applied to the P-type source region, and a negative voltage is applied to the P-type drain region.

摘要翻译： 提供了一种用于编程具有N阱，浮动栅极，控制栅极，P型源极区域和P型漏极区域的P沟道EEPROM的方法。 在该方法中，N阱接地，第一正电压施加到控制栅极，第二正电压或编程电流施加到P型源极区域，负电压施加到P- 型漏极区域。

公开(公告)号：US20050153543A1

公开(公告)日：2005-07-14

申请号：US10753657

申请日：2004-01-08

申请人： Shui-Chin Huang ,  Chien-Hung Chen

发明人： Shui-Chin Huang ,  Chien-Hung Chen

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8247

CPC分类号： H01L27/11521 ,  H01L21/76897

摘要： A self-aligned contact method includes, firstly, forming a plurality of stack structures on a semiconductor substrate. The stack structures separate each other and each has a first polysilicon layer, an insulating layer on the first polysilicon layer and a second polysilicon layer on the insulating layer. Secondly, a spacer forms on the sidewall of the stack structures, and then a dielectric layer is formed on the stack structures, the spacers and the semiconductor substrate. Finally, the portion of the second polysilicon layer is used as a buffer for forming a contact window by removing a portion of the dielectric layer. The contact window is located between two stack structures.

摘要翻译： 自对准接触方法首先在半导体衬底上形成多个堆叠结构。 堆叠结构彼此分离，并且每个具有第一多晶硅层，第一多晶硅层上的绝缘层和绝缘层上的第二多晶硅层。 其次，在堆叠结构的侧壁上形成间隔物，然后在堆叠结构，间隔物和半导体衬底上形成介电层。 最后，通过去除电介质层的一部分，将第二多晶硅层的部分用作形成接触窗的缓冲器。 接触窗口位于两个堆叠结构之间。

公开(公告)号：US20050116262A1

公开(公告)日：2005-06-02

申请号：US10728137

申请日：2003-12-03

申请人： Chen-Hung Chen ,  Shui-Chin Huang

发明人： Chen-Hung Chen ,  Shui-Chin Huang

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L27/115 ,  H01L29/768

CPC分类号： G11C16/10 ,  G11C16/0433 ,  H01L27/115

摘要： A method for programming a P-channel EEPROM having an N-well, a floating gate, a control gate, a P-type source region and a P-type drain region is provided. In the method, the N-well is grounded, a first positive voltage is applied to the control gate, a second positive voltage or a programming current is applied to the P-type source region, and a negative voltage is applied to the P-type drain region.

摘要翻译： 提供了一种用于编程具有N阱，浮动栅极，控制栅极，P型源极区域和P型漏极区域的P沟道EEPROM的方法。 在该方法中，N阱接地，第一正电压施加到控制栅极，第二正电压或编程电流施加到P型源极区域，负电压施加到P- 型漏极区域。

公开(公告)号：US06831335B2

公开(公告)日：2004-12-14

申请号：US10410975

申请日：2003-04-09

申请人： Shui-Chin Huang

发明人： Shui-Chin Huang

IPC分类号： H01L218246

CPC分类号： H01L27/1122 ,  H01L27/112 ,  H01L27/1126

摘要： A method of fabricating a memory device having a buried source/drain region is provided, in which a dielectric layer and a word-line is sequentially formed on the substrate, then a buried source/drain region is formed in the substrate. After that, a barrier layer is formed on the exposed surface of the word-line, then a metal layer is formed over the substrate. The metal layer is patterned to leave a portion covering the buried source/drain region beside the word-line and crossing over the word-line.

摘要翻译： 提供一种制造具有掩埋源极/漏极区域的存储器件的方法，其中介电层和字线顺序地形成在衬底上，然后在衬底中形成掩埋的源极/漏极区域。 之后，在字线的暴露表面上形成阻挡层，然后在衬底上形成金属层。 金属层被图案化以留下在字线旁边覆盖掩埋源极/漏极区的部分并跨越字线。