公开(公告)号：US06940321B2

公开(公告)日：2005-09-06

申请号：US10728630

申请日：2003-12-05

申请人： Nak-Won Heo ,  Chang-Sik Yoo

发明人： Nak-Won Heo ,  Chang-Sik Yoo

IPC分类号： G11C11/40 ,  G11C7/10 ,  G11C7/22 ,  H03B1/00 ,  H03B3/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22

摘要： Provided is a circuit for generating a data strobe signal used in a double data rate (DDR) synchronous semiconductor device. The circuit comprises a first logic unit capable of generating a pull up control signal responsive to first and second clock signals. A second logic unit is capable of generating a pull down signal responsive to the first and second clock signals. A data strobe buffer is capable of generating a data strobe signal responsive to the pull up and pull down control signals, the data strobe signal including a preamble. The first logic unit is capable of generating the preamble responsive to a first pulse of the first clock signal. And the data strobe signal is in a high impedance state responsive to a last pulse of the first clock signal.

摘要翻译： 提供了一种用于产生在双倍数据速率（DDR）同步半导体器件中使用的数据选通信号的电路。 电路包括能够响应于第一和第二时钟信号产生上拉控制信号的第一逻辑单元。 第二逻辑单元能够响应于第一和第二时钟信号产生下拉信号。 数据选通缓冲器能够响应于上拉和下拉控制信号产生数据选通信号，数据选通信号包括前导码。 第一逻辑单元能够响应于第一时钟信号的第一脉冲而产生前导码。 并且数据选通信号响应于第一时钟信号的最后脉冲处于高阻抗状态。

公开(公告)号：US07558127B2

公开(公告)日：2009-07-07

申请号：US12105209

申请日：2008-04-17

申请人： Nak-Won Heo ,  Chang-Sik Yoo

发明人： Nak-Won Heo ,  Chang-Sik Yoo

IPC分类号： G11C7/00 ,  G11C11/34 ,  G06F12/00 ,  G06F13/00

CPC分类号： G11C7/1066 ,  G11C7/1039 ,  G11C7/1051 ,  G11C2207/107

摘要： Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

摘要翻译： 本发明的实施例包括可以从流水线电路中的多个锁存器并行读取数据的数据输出电路。 偶数数据和奇数数据同时在单个时钟周期输出，然后被转换成DDR数据，然后被串行输出。 通过以这种方式移动数据，与常规数据输出电路相比，本发明的实施例可以将所需控制信号的数量减少多达50％。

公开(公告)号：US07376021B2

公开(公告)日：2008-05-20

申请号：US10411724

申请日：2003-04-11

申请人： Nak-Won Heo ,  Chang-Sik Yoo

发明人： Nak-Won Heo ,  Chang-Sik Yoo

IPC分类号： G11C7/00 ,  G11C11/34 ,  G06F12/00 ,  G06F13/00

CPC分类号： G11C7/1066 ,  G11C7/1039 ,  G11C7/1051 ,  G11C2207/107

摘要： Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

摘要翻译： 本发明的实施例包括可以从流水线电路中的多个锁存器并行读取数据的数据输出电路。 偶数数据和奇数数据同时在单个时钟周期输出，然后被转换成DDR数据，然后被串行输出。 通过以这种方式移动数据，与常规数据输出电路相比，本发明的实施例可以将所需控制信号的数量减少多达50％。

公开(公告)号：US08184048B2

公开(公告)日：2012-05-22

申请号：US12393107

申请日：2009-02-26

申请人： Chang-Sik Yoo ,  Jun-Gi Jo ,  Seong-Eon Park

发明人： Chang-Sik Yoo ,  Jun-Gi Jo ,  Seong-Eon Park

IPC分类号： G01S19/33 ,  G01S19/40

CPC分类号： H03G3/3052 ,  G01S19/33 ,  G01S19/37 ,  H03G7/001

摘要： A dual mode satellite signal receiver capable of supporting at least two global navigation satellite systems and a satellite signal receiving method are provided. The dual mode satellite signal receiver comprises a frequency synthesizer for generating a local oscillator signal based on a reference frequency; a mixer for mixing the local oscillator signal with a satellite signal and outputting the mixed signal as a signal of an intermediate frequency band; a first filter for filtering the signal output from the mixer to reject an image signal and output only an actual signal; a second filter for filtering the actual signal to output only a predetermined bandwidth according to a positioning mode; and an amplifier for amplifying the second filter output signal to a predetermined level and outputting the amplified signal.

摘要翻译： 提供了能够支持至少两个全球导航卫星系统和卫星信号接收方法的双模卫星信号接收机。 双模式卫星信号接收机包括用于基于参考频率产生本地振荡器信号的频率合成器; 混合器，用于将本地振荡器信号与卫星信号混合并输出混合信号作为中频带的信号; 用于对从混频器输出的信号进行滤波以拒绝图像信号并仅输出实际信号的第一滤波器; 第二滤波器，用于根据定位模式对实际信号进行滤波以仅输出预定带宽; 以及用于将第二滤波器输出信号放大到预定电平并输出放大信号的放大器。

公开(公告)号：US07826583B2

公开(公告)日：2010-11-02

申请号：US11819807

申请日：2007-06-29

申请人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

发明人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

IPC分类号： H03D3/24 ,  H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H03D13/004

摘要： A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.

摘要翻译： 时钟数据恢复装置包括相位循环单元，电压控制延迟线，相位检测单元，电荷泵单元和环路滤波器单元。 相位循环单元输出相位不同的多个时钟信号，其频率低于数据的时钟信号。 电压控制延迟线通过根据输入电压电平延迟时钟信号来输出恢复的时钟信号。 相位检测单元分别与时钟信号同步地输出恢复的数据，并通过将恢复的时钟信号与数据进行比较，输出比数据宽的脉冲宽度的增减信号。 电荷泵单元响应于增量和减量信号输出相应的电流。 环路滤波器单元通过输出电压来确定电压控制延迟线中的延迟量。

公开(公告)号：US20080101524A1

公开(公告)日：2008-05-01

申请号：US11819807

申请日：2007-06-29

申请人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

发明人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

IPC分类号： H03D3/24

CPC分类号： H03D13/004

摘要： A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.

摘要翻译： 时钟数据恢复装置包括相位循环单元，电压控制延迟线，相位检测单元，电荷泵单元和环路滤波器单元。 相位循环单元输出相位不同的多个时钟信号，其频率低于数据的时钟信号。 电压控制延迟线通过根据输入电压电平延迟时钟信号来输出恢复的时钟信号。 相位检测单元分别与时钟信号同步地输出恢复的数据，并通过将恢复的时钟信号与数据进行比较，输出比数据宽的脉冲宽度的增减信号。 电荷泵单元响应于增量和减量信号输出相应的电流。 环路滤波器单元通过输出电压来确定电压控制延迟线中的延迟量。

公开(公告)号：US07894260B2

公开(公告)日：2011-02-22

申请号：US12195516

申请日：2008-08-21

申请人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

发明人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/105

摘要： A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

摘要翻译： 具有片上终端（ODT）电路和ODT方法的同步半导体存储器件通过执行与外部同步的ODT操作，满足ODT DC和AC参数规格并通过外部或内部控制执行自适应阻抗匹配 时钟。 具有用于与外部时钟同步地进行数据输出操作的数据输出电路的同步半导体存储器件包括ODT电路，用于产生具有与用于数据输出操作的数据输出上下信号相同的定时的ODT上下信号， 执行ODT操作。

公开(公告)号：US20090219204A1

公开(公告)日：2009-09-03

申请号：US12393107

申请日：2009-02-26

申请人： Chang-Sik Yoo ,  Jun-Gi Jo ,  Seong-Eon Park

发明人： Chang-Sik Yoo ,  Jun-Gi Jo ,  Seong-Eon Park

IPC分类号： G01S1/00

CPC分类号： H03G3/3052 ,  G01S19/33 ,  G01S19/37 ,  H03G7/001

摘要： A dual mode satellite signal receiver capable of supporting at least two global navigation satellite systems and a satellite signal receiving method are provided. The dual mode satellite signal receiver comprises a frequency synthesizer for generating a local oscillator signal based on a reference frequency; a mixer for mixing the local oscillator signal with a satellite signal and outputting the mixed signal as a signal of an intermediate frequency band; a first filter for filtering the signal output from the mixer to reject an image signal and output only an actual signal; a second filter for filtering the actual signal to output only a predetermined bandwidth according to a positioning mode; and an amplifier for amplifying the second filter output signal to a predetermined level and outputting the amplified signal.

摘要翻译： 提供了能够支持至少两个全球导航卫星系统和卫星信号接收方法的双模卫星信号接收机。 双模式卫星信号接收机包括用于基于参考频率产生本地振荡器信号的频率合成器; 混合器，用于将本地振荡器信号与卫星信号混合并输出混合信号作为中频带的信号; 用于对从混频器输出的信号进行滤波以拒绝图像信号并仅输出实际信号的第一滤波器; 第二滤波器，用于根据定位模式对实际信号进行滤波以仅输出预定带宽; 以及用于将第二滤波器输出信号放大到预定电平并输出放大信号的放大器。

公开(公告)号：US07426145B2

公开(公告)日：2008-09-16

申请号：US11802443

申请日：2007-05-23

申请人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

发明人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

IPC分类号： G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/105

摘要： A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

摘要翻译： 具有片上终端（ODT）电路和ODT方法的同步半导体存储器件通过执行与外部同步的ODT操作，满足ODT DC和AC参数规格并通过外部或内部控制执行自适应阻抗匹配 时钟。 具有用于与外部时钟同步地进行数据输出操作的数据输出电路的同步半导体存储器件包括ODT电路，用于产生具有与用于数据输出操作的数据输出上下信号相同的定时的ODT上下信号， 执行ODT操作。

公开(公告)号：US20110169591A1

公开(公告)日：2011-07-14

申请号：US12684876

申请日：2010-01-08

申请人： Sinn-Young Kim ,  Chang-Sik Yoo

发明人： Sinn-Young Kim ,  Chang-Sik Yoo

IPC分类号： H03H7/01

CPC分类号： H03H11/1291 ,  H03H11/04

摘要： A filter cut-off frequency correction circuit, inputted with a step function increasing from a first voltage to a second voltage, comprises a linear passive filter, for integrating the step function to obtain a third voltage; a first comparator, outputting a first high-level signal when the third voltage is greater than a first predetermined reference voltage; a second comparator, outputting a second high-level signal in a first period from the time that the second voltage is applied to the time that the first comparator outputs the first high-level signal; a counter, for counting a number of clock pulses of a reference clock inputted in the first period; a digital block, for calculating a variation rate of time constant according to the number of clock pulses of the reference clock, and generating a correction code; and a filter, for correcting the cut-off frequency according to the correction code. The correction circuit can improve the speed of cut-off frequency adjustment.

摘要翻译： 输入从第一电压增加到第二电压的阶梯函数的滤波器截止频率校正电路包括线性无源滤波器，用于积分步长函数以获得第三电压; 第一比较器，当第三电压大于第一预定参考电压时，输出第一高电平信号; 第二比较器，从施加所述第二电压的时间到所述第一比较器输出所述第一高电平信号的时间的第一时段中输出第二高电平信号; 计数器，用于计数在第一周期中输入的参考时钟的数量的时钟脉冲; 数字块，用于根据参考时钟的时钟脉冲数来计算时间常数的变化率，并产生校正码; 以及滤波器，用于根据校正码校正截止频率。 校正电路可以提高截止频率调节的速度。