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公开(公告)号：US20070006007A1
公开(公告)日：2007-01-04
申请号：US11173218
申请日：2005-06-30
申请人： Nancy Woodbridge , Mark Fullerton , Amit Dor , Vasudev Bibikar , Rajith Mavila
发明人： Nancy Woodbridge , Mark Fullerton , Amit Dor , Vasudev Bibikar , Rajith Mavila
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.
摘要翻译： 电子电路包括至少一个数字逻辑电路; 和电源控制电路。 功率控制电路可操作以响应于提供给至少一个数字逻辑电路的时钟频率的变化来调节提供给至少一个数字逻辑电路的功率信号的电压。 在另一实施例中，功率控制器可操作以在频率增加之前增加施加到数字逻辑电路的功率信号的电压，并且可操作地降低施加到数字逻辑电路之后的功率信号的电压 频率下降。
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公开(公告)号：US07603575B2
公开(公告)日：2009-10-13
申请号：US11173218
申请日：2005-06-30
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.
摘要翻译： 电子电路包括至少一个数字逻辑电路; 和电源控制电路。 功率控制电路可操作以响应于提供给至少一个数字逻辑电路的时钟频率的变化来调节提供给至少一个数字逻辑电路的功率信号的电压。 在另一实施例中，功率控制器可操作以在频率增加之前增加施加到数字逻辑电路的功率信号的电压，并且可操作地降低施加到数字逻辑电路之后的功率信号的电压 频率下降。
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公开(公告)号：US20060200684A1
公开(公告)日：2006-09-07
申请号：US11069924
申请日：2005-03-01
申请人： Vasudev Bibikar , Rajith Mavila
发明人： Vasudev Bibikar , Rajith Mavila
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A computerized system includes at least one digital logic circuit and a power control circuit. The power control circuit is operable to reduce the voltage of a power signal applied to the at least one digital logic circuit, operable to bring the digital logic circuit from a high power level to a low power level, and operable to increase the voltage of the power signal applied to the digital logic circuit before bringing the digital logic circuit from a low power level to a high power level.
摘要翻译： 计算机化系统包括至少一个数字逻辑电路和功率控制电路。 功率控制电路可操作以减少施加到至少一个数字逻辑电路的功率信号的电压，可操作以将数字逻辑电路从高功率电平提供到低功率电平，并且可操作以增加 将数字逻辑电路从低功率电平提供到高功率电平之前施加到数字逻辑电路的功率信号。
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