摘要:
Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
摘要:
An apparatus and method are disclosed to combine pad functionality in an integrated circuit. A power, ground, or signal pad is connected to a power, ground, or signal source, respectively. The power, ground, or signal pad is additionally connected to an additional signal source, such as automatic test equipment in a testing environment. By temporarily disconnecting either the power, ground, or signal source, from the functional block within the integrated circuit to which the source is delivered, the same pad may pass in another signal to other portions of the integrated circuit. In the alternative, the same pad may pass in another signal to other portions of the integrated circuit without disconnecting the original signal by coupling the additional signal over the original signal. Further, combining pad functionality enables reuse of an input pad as an output pad for signals originating from within the integrated circuit.
摘要:
Embodiments include a system and method for an interrupt controller that propagates interrupts to a subsystem in a system-on-a-chip (SOC). Interrupts are provided to an interrupt controller that controls access of interrupts to a particular subsystem in the SOC that includes multiple subsystems. Each subsystem in the SOC generates multiple interrupts to other subsystems in the SOC. The interrupt controller processes multiple interrupts and generates an interrupt output. The interrupt output is then transmitted to a particular subsystem.
摘要:
An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.
摘要:
Briefly, a method an apparatus of a power management system of a semiconductor device capable of managing a power consumption of the semiconductor device by varying an operating voltage of the semiconductor device according to a voltage value based on a reference number.
摘要:
A technique includes sharing common external terminals of a memory device to communicate data and an address with the memory device for a given memory operation. Different sets of address bits indicative of the address are communicated over the common external terminals at different times.
摘要:
A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults.