公开(公告)号：US07257026B2

公开(公告)日：2007-08-14

申请号：US11418017

申请日：2006-05-05

申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

摘要翻译： 在其中设置多个阈值以将多电平数据存储在存储单元中的非易失性半导体存储器件中，根据地址信号或控制信号将多位数据的位分别写入存储器单元 阅读和删除。 具体地说，存储器阵列被构造成可以通过X，Y和Z的三维地址来访问，存储器单元中的多位数据由Z地址区分。

公开(公告)号：US20050013167A1

公开(公告)日：2005-01-20

申请号：US10920311

申请日：2004-08-18

申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

IPC分类号： G11C11/56 ,  G11C11/34

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

摘要翻译： 在其中设置多个阈值以将多电平数据存储在存储单元中的非易失性半导体存储器件中，根据地址信号或控制信号将多位数据的位分别写入存储器单元 阅读和删除。 具体地说，存储器阵列被构造成可以通过X，Y和Z的三维地址来访问，存储器单元中的多位数据由Z地址区分。

公开(公告)号：US6166950A

公开(公告)日：2000-12-26

申请号：US117369

申请日：1998-07-28

申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

IPC分类号： G11C11/56 ,  G11C11/34

CPC分类号： G11C11/5628 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08

摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

摘要翻译： PCT No.PCT / JP96 / 01907 Sec。 371日期：1998年7月28日 102（e）1998年7月28日PCT PCT 1996年7月10日PCT公布。 公开号WO98 / 01861 日期1998年1月15日在其中设定多个阈值以将多电平数据存储在存储单元中的非易失性半导体存储器件中，多位数据的位根据地址信号被单独写入存储单元， 一个控制信号来实现读取和擦除。 具体地说，存储器阵列被构造成可以通过X，Y和Z的三维地址来访问，存储器单元中的多位数据由Z地址区分。

公开(公告)号：US07079416B2

公开(公告)日：2006-07-18

申请号：US11041233

申请日：2005-01-25

申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

摘要翻译： 在其中设置多个阈值以将多电平数据存储在存储单元中的非易失性半导体存储器件中，根据地址信号或控制信号将多位数据的位分别写入存储器单元 阅读和删除。 具体地说，存储器阵列被构造成可以通过X，Y和Z的三维地址来访问，存储器单元中的多位数据由Z地址区分。

公开(公告)号：US06788572B2

公开(公告)日：2004-09-07

申请号：US10455409

申请日：2003-06-06

申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

IPC分类号： G11C1134

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

摘要翻译： 在其中设置多个阈值以将多电平数据存储在存储单元中的非易失性半导体存储器件中，根据地址信号或控制信号将多位数据的位分别写入存储器单元 阅读和删除。 具体地说，存储器阵列被构造成可以通过X，Y和Z的三维地址来访问，存储器单元中的多位数据由Z地址区分。

公开(公告)号：US06590808B1

公开(公告)日：2003-07-08

申请号：US10288334

申请日：2002-11-06

申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

IPC分类号： G11C1134

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

公开(公告)号：US06496411B2

公开(公告)日：2002-12-17

申请号：US10024722

申请日：2001-12-21

申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

IPC分类号： G11C1134

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

公开(公告)号：US20060221685A1

公开(公告)日：2006-10-05

申请号：US11418017

申请日：2006-05-05

申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

公开(公告)号：US20050122803A1

公开(公告)日：2005-06-09

申请号：US11041233

申请日：2005-01-25

申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

IPC分类号： G11C11/56 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

摘要翻译： 在其中设置多个阈值以将多电平数据存储在存储单元中的非易失性半导体存储器件中，根据地址信号或控制信号将多位数据的位分别写入存储器单元 阅读和删除。 具体地说，存储器阵列被构造成可以通过X，Y和Z的三维地址来访问，存储器单元中的多位数据由Z地址区分。

公开(公告)号：US06335878B1

公开(公告)日：2002-01-01

申请号：US09706689

申请日：2000-11-07

申请人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

发明人： Naoki Yamada ,  Hiroshi Sato ,  Tetsuya Tsujikawa ,  Kazuyuki Miyazawa

IPC分类号： G11C1134

CPC分类号： G11C16/0483 ,  G11C7/1006 ,  G11C8/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

摘要翻译： 在其中设置多个阈值以将多电平数据存储在存储单元中的非易失性半导体存储器件中，根据地址信号或控制信号将多位数据的位分别写入存储器单元 阅读和删除。 具体地说，存储器阵列被构造成可以通过X，Y和Z的三维地址来访问，存储器单元中的多位数据由Z地址区分。