公开(公告)号：US20100303163A1

公开(公告)日：2010-12-02

申请号：US12782018

申请日：2010-05-18

申请人： Naoto ADACHI

发明人： Naoto ADACHI

IPC分类号： H04L27/06 ,  H04L27/22 ,  H04J11/00 ,  H04L27/28

CPC分类号： H04L27/0008 ,  H04L27/265 ,  H04L27/2662

摘要： A demodulating circuit includes: a fast Fourier transform circuit which fast Fourier transforms a received signal and outputs a plurality of carrier signals; an output selecting circuit which selects at least two signals from the plurality of carrier signals, the at least two signals including a first signal modulated in accordance with a first modulation method and a second signal modulated in accordance with a second modulation method; an inverse fast Fourier transform circuit which inverse Fourier transforms transmission path characteristic values including a first transmission path characteristic value obtained based on the first signal and a second transmission path characteristic value obtained based on the second signal; and an FFT window control circuit which controls a position of an FFT window based on the inverse Fourier transformed transmission path characteristic values.

摘要翻译： 解调电路包括：快速傅立叶变换电路，其快速傅里叶变换接收信号并输出​​多个载波信号; 输出选择电路，其从所述多个载波信号中选择至少两个信号，所述至少两个信号包括根据第一调制方法调制的第一信号和根据第二调制方法调制的第二信号; 逆傅里叶变换电路，其对包括基于第一信号获得的第一传输路径特性值和基于第二信号获得的第二传输路径特性值的传输路径特性值进行逆傅立叶变换; 以及FFT窗口控制电路，其基于傅里叶逆变换的传输路径特征值来控制FFT窗口的位置。

公开(公告)号：US20090285086A1

公开(公告)日：2009-11-19

申请号：US12346450

申请日：2008-12-30

申请人： Naoto ADACHI

发明人： Naoto ADACHI

IPC分类号： H04J11/00

CPC分类号： H04L27/2672 ,  H04L25/0232 ,  H04L25/03159 ,  H04L27/2665 ,  H04L27/2676

摘要： An FFT unit generates a frequency domain signal by converting an OFDM signal using Fourier transform. A delay amount calculation unit generates a delay profile of the OFDM signal. The control determination unit detects a main wave and an interference wave using the delay profile. When the time difference between the main wave and a preceding wave is larger than a guard interval of the OFDM signal, an FFT window control unit sets the start position of the FFT window at a position shifted forward from the symbol start position of the main wave by an amount corresponding to the guard interval.

摘要翻译： FFT单元通过使用傅里叶变换转换OFDM信号来生成频域信号。 延迟量计算单元生成OFDM信号的延迟分布。 控制确定单元使用延迟分布来检测主波和干扰波。 当主波和前一波之间的时间差大于OFDM信号的保护间隔时，FFT窗口控制单元将FFT窗口的开始位置设置在从主波的符号开始位置向前移位的位置 相当于保护间隔的量。

公开(公告)号：US20070288832A1

公开(公告)日：2007-12-13

申请号：US11554811

申请日：2006-10-31

申请人： Naoto ADACHI

发明人： Naoto ADACHI

IPC分类号： H03M13/00

CPC分类号： H03M13/27 ,  H03M13/6325 ,  H03M13/6505 ,  H04L1/0045 ,  H04L1/0071 ,  H04L27/2649

摘要： A receiver that receives a digital signal transmitted on the basis of an orthogonal frequency division multiplexing (OFDM) method. This receiver comprises a demodulation unit for demodulating the digital signal, a demapping unit for demapping demodulated data output from the demodulation unit, a frequency deinterleave unit for executing a frequency deinterleaving process on data output from the demapping unit, a delay unit for delaying control information superposed on the digital signal by a prescribed time period, and a time deinterleave unit for executing, on the basis of the interleave length specified by the control information delayed by the delay unit, a time deinterleaving process on data on which the frequency deinterleaving process has been executed.

摘要翻译： 一种接收器，其接收基于正交频分复用（OFDM）方法发送的数字信号。 该接收机包括用于解调数字信号的解调单元，用于解映射从解调单元输出的解调数据的解映射单元，用于对从解映射单元输出的数据执行频率去交织处理的频率解交织单元，用于延迟控制信息的延迟单元 在数字信号上叠加规定的时间段的时间解交织单元，以及根据由延迟单元延迟的控制信息指定的交织长度，对频率解交织处理具有的数据进行时间解交织处理的时间解交织单元 被执行

公开(公告)号：US20110004806A1

公开(公告)日：2011-01-06

申请号：US12829847

申请日：2010-07-02

申请人： Naoto ADACHI

发明人： Naoto ADACHI

IPC分类号： H03M13/27 ,  G06F11/10 ,  H03M13/45

CPC分类号： H03M13/2782 ,  H03M13/2789 ,  H03M13/2936 ,  H03M13/41 ,  H03M13/6306 ,  H04L1/0052 ,  H04L1/0054 ,  H04L1/0071 ,  H04L27/2647

摘要： A data receiving circuit includes: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-processed; a memory configured to be shared by the first de-interleave circuit and the second de-interleave circuit and store respective hard decision information and respective soft decision information of the first data and the second data; and a memory control circuit configured to vary a first through fourth number of bits stored in the memory, the first number corresponding to the hard decision information of the first data, the second number corresponding to the soft decision information of the first data, the third number corresponding to the hard decision information of the second data, the fourth number corresponding to the soft decision information of the second data.

摘要翻译： 数据接收电路包括：第一解交织电路，被配置为对被解调并进行软判决处理的第一数据进行解交织; 第二解交织电路，被配置为对被解调并被软判决处理的第二数据进行解交织; 存储器，被配置为由所述第一解交织电路和所述第二解交织电路共享，并且存储所述第一数据和所述第二数据的相应硬判决信息和相应的软判决信息; 以及存储器控制电路，被配置为改变存储在存储器中的第一到第四位数，对应于第一数据的硬判决信息的第一数，对应于第一数据的软判决信息的第二数，第三数 与第二数据的硬判决信息相对应的数字，第四数字对应于第二数据的软判决信息。

公开(公告)号：US20090285318A1

公开(公告)日：2009-11-19

申请号：US12346491

申请日：2008-12-30

申请人： Naoto ADACHI

发明人： Naoto ADACHI

IPC分类号： H04H20/71

CPC分类号： H04H60/12 ,  H04H20/33

摘要： An FFT unit generates a frequency-domain signal for one-segment broadcasting and a frequency-domain signal for full-segment broadcasting. Under a good reception environment, the frequency-domain signal for the full-segment broadcasting is extracted by a switching control unit and the transmitted data for the full-segment broadcasting are recovered. When the reception environment deteriorates, both the one-segment broadcasting and the full-segment broadcasting are temporary demodulated. After a delay time due to the demodulation process has passed, a reception mode is switched from the full-segment broadcasting to the one-segment broadcasting.

摘要翻译： FFT单元产生用于单段广播的频域信号和用于全分段广播的频域信号。 在良好的接收环境下，全分段广播的频域信号由切换控制单元提取，并且全段广播的发送数据被恢复。 当接收环境恶化时，单段广播和全频段广播都被临时解调。 在经过解调处理的延迟时间之后，将接收模式从全分段广播切换到单分段广播。

公开(公告)号：US20120307944A1

公开(公告)日：2012-12-06

申请号：US13442572

申请日：2012-04-09

申请人： Hiroaki TAKAGI ,  Naoto ADACHI ,  Masataka Umeda

发明人： Hiroaki TAKAGI ,  Naoto ADACHI ,  Masataka Umeda

IPC分类号： H04L27/06

CPC分类号： H04L25/03821 ,  H04L27/2665 ,  H04L27/2675 ,  H04L27/2691

摘要： A receiving apparatus includes a symbol timing detection unit, a Fourier transform unit, a first symbol timing correction unit, and an interpolation synthesis unit. The symbol timing detection unit is configured to detect a Fourier transform start position from a received transmitting signal of a symbol unit, the Fourier transform unit is configured to perform a Fourier transform using the detected Fourier transform start position. The first symbol timing correction unit is configured to calculate and correct an amount of change between the Fourier transform start position of a reference symbol and the detected Fourier transform start position, and the interpolation synthesis unit is configured to perform an interpolation synthesis of a plurality of delay profiles corresponding to a plurality of symbols including the reference symbol and a symbol in which the amount of change is corrected.

摘要翻译： 接收装置包括符号定时检测单元，傅里叶变换单元，第一符号定时校正单元和内插合成单元。 符号定时检测单元被配置为从接收到的符号单元的发送信号检测傅立叶变换开始位置，傅立叶变换单元被配置为使用检测的傅立叶变换开始位置进行傅里叶变换。 第一符号定时校正单元被配置为计算和校正参考符号的傅立叶变换开始位置与检测到的傅里叶变换起始位置之间的变化量，并且内插合成单元被配置为执行多个 对应于包括参考符号的多个符号的延迟分布和其中改变量的符号。

公开(公告)号：US20120300883A1

公开(公告)日：2012-11-29

申请号：US13442443

申请日：2012-04-09

申请人： Naoto ADACHI ,  Masataka UMEDA

发明人： Naoto ADACHI ,  Masataka UMEDA

IPC分类号： H04L27/06

CPC分类号： H04L25/067 ,  H04L1/0054 ,  H04L25/0232 ,  H04L2025/03414 ,  H04L2025/0342

摘要： A demodulation circuit includes a hard decision process unit and a soft decision process unit. The hard decision process unit is configured to perform a hard decision process using a demodulated signal, and the demodulated signal is a demodulated received signal. The soft decision process unit is configured to determine a range of assignment with respect to a transitioning part in the demodulated signal, calculate a likelihood value of a bit, and perform a soft decision process.

摘要翻译： 解调电路包括硬决策处理单元和软决策处理单元。 硬决策处理单元被配置为使用解调信号执行硬判决处理，并且解调信号是解调的接收信号。 软决策处理单元被配置为确定相对于解调信号中的转换部分的分配范围，计算比特的似然值，并执行软判决处理。

公开(公告)号：US20090097576A1

公开(公告)日：2009-04-16

申请号：US12181782

申请日：2008-07-29

申请人： Naoto ADACHI ,  Makoto Hamaminato

发明人： Naoto ADACHI ,  Makoto Hamaminato

IPC分类号： H04L27/28 ,  H04L27/06

CPC分类号： H04L27/2688 ,  H04L27/2665 ,  H04L27/2675 ,  H04L27/2678

摘要： A receiver circuit in each branch has an FFT unit that performs Fourier transform on OFDM signals. A slave branch FFT window control unit determines whether an undesired wave is a preceding wave or a delay wave, and notifies a master branch of the result. In response to the notification from the slave branch, a master branch FFT window control unit controls a position of an FFT window that indicates a time range in which Fourier transform is performed on OFDM signals.

摘要翻译： 每个分支中的接收机电路具有对OFDM信号进行傅里叶变换的FFT单元。 从分支FFT窗口控制单元确定不需要的波是前一波还是延迟波，并通知主分支结果。 响应于从分支的通知，主分支FFT窗口控制单元控制指示对OFDM信号进行傅里叶变换的时间范围的FFT窗口的位置。

公开(公告)号：US20070280364A1

公开(公告)日：2007-12-06

申请号：US11554869

申请日：2006-10-31

申请人： Naoto ADACHI

发明人： Naoto ADACHI

IPC分类号： H04K1/10

CPC分类号： H04L27/2662 ,  H04L5/0007 ,  H04L25/03343 ,  H04L27/2665

摘要： An OFDM receiver according to the present invention judges whether or not a delay amount (i.e., a first delay amount) of a transmission path detected from scattered pilot information existing in an OFDM signal of a frequency domain by referring to peak position information obtainable from OFDM signals of the preceding and following symbols, calculates another delay amount (i.e., a second delay amount) from the delay amount (i.e., the first delay amount) if the aforementioned delay amount is judged to be inappropriate, and set a position of a time window by using the calculated delay amount.

摘要翻译： 根据本发明的OFDM接收机通过参考从OFDM获得的峰值位置信息判断从存在于频域的OFDM信号中的分散导频信息中检测到的传输路径的延迟量（即，第一延迟量） 如果前述延迟量被判断为不适当，则从延迟量（即，第一延迟量）计算另一延迟量（即，第二延迟量），并且设置时间的位置 窗口通过使用计算的延迟量。

公开(公告)号：US20070274406A1

公开(公告)日：2007-11-29

申请号：US11560508

申请日：2006-11-16

申请人： Naoto ADACHI

发明人： Naoto ADACHI

IPC分类号： H04K1/10 ,  H04B1/10

CPC分类号： H04L27/261 ,  H04L25/03006

摘要： A carrier interpolation unit (a digital filter) performs interpolation processing of SP signal in the frequency domain. An IFFT circuit converts a frequency-domain signal into a time-domain signal. A delay profile generation unit generates a delay profile based on an output of the IFFT circuit. The filter control unit controls a pass band of the digital filter in accordance with the delay profile. An FFT window control unit controls a position of a window to extract a calculation range of FFT in accordance with the delay profile. When delay time of multipath is larger than the guard interval, and when the reception power of the interference wave is larger than a threshold, the pass band of the digital filter is minimized.

摘要翻译： 载波插值单元（数字滤波器）在频域中执行SP信号的内插处理。 IFFT电路将频域信号转换成时域信号。 延迟分布生成单元基于IFFT电路的输出生成延迟分布。 滤波器控制单元根据延迟分布控制数字滤波器的通带。 FFT窗口控制单元根据延迟分布控制窗口的位置以提取FFT的计算范围。 当多路径的延迟时间大于保护间隔时，并且当干扰波的接收功率大于阈值时，数字滤波器的通带被最小化。