公开(公告)号：US07166901B2

公开(公告)日：2007-01-23

申请号：US10950828

申请日：2004-09-27

申请人： Naoto Inoue ,  Hitomi Sakurai ,  Min Paek ,  Sang Yeon Kim ,  In Ki Kim

发明人： Naoto Inoue ,  Hitomi Sakurai ,  Min Paek ,  Sang Yeon Kim ,  In Ki Kim

IPC分类号： H01L29/00

CPC分类号： H01L27/0921 ,  H01L21/76237 ,  H01L21/823814 ,  H01L21/823878

摘要： A semiconductor device comprises a semiconductor substrate having a high voltage region and a low voltage region, at least a pair of adjacent high voltage MOS transistors disposed on the high voltage region of the semiconductor substrate, and low voltage MOS transistors disposed on the low voltage region of the semiconductor substrate. A first element isolator comprises a first shallow trench disposed on a surface of the low voltage, region of the semiconductor substrate, and a first dielectric embedded in the first shallow trench. A pair of second element isolators comprises two second shallow trenches spaced apart at an interval between a source region or a drain region of the pair of the adjacent high voltage MOS transistors and a source or a drain region of the other of the pair of the adjacent high voltage MOS transistors, and a second dielectric embedded in each of the second shallow trenches. The second shallow trenches are disposed on a surface of the high voltage region of the semiconductor substrate. A channel cut region having a high impurity concentration is disposed on the surface of the substrate between the second shallow trenches.

摘要翻译： 半导体器件包括具有高电压区域和低电压区域的半导体衬底，设置在半导体衬底的高电压区域上的至少一对相邻的高压MOS晶体管和设置在低电压区域上的低压MOS晶体管 的半导体衬底。 第一元件隔离器包括设置在半导体衬底的低电压区域的表面上的第一浅沟槽和嵌入在第一浅沟槽中的第一电介质。 一对第二元件隔离器包括在一对相邻高压MOS晶体管的源极区域或漏极区域之间间隔开的两个第二浅沟槽和一对相邻的高压MOS晶体管中的另一个的源极或漏极区域 高电压MOS晶体管和嵌入在每个第二浅沟槽中的第二电介质。 第二浅沟槽设置在半导体衬底的高压区域的表面上。 具有高杂质浓度的沟道切割区域设置在第二浅沟槽之间的衬底表面上。

公开(公告)号：US20050116265A1

公开(公告)日：2005-06-02

申请号：US10950828

申请日：2004-09-27

申请人： Naoto Inoue ,  Hitomi Sakurai ,  Min Paek ,  Sang Kim ,  In Kim

发明人： Naoto Inoue ,  Hitomi Sakurai ,  Min Paek ,  Sang Kim ,  In Kim

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/76

CPC分类号： H01L27/0921 ,  H01L21/76237 ,  H01L21/823814 ,  H01L21/823878

摘要： In a semiconductor device in which high voltage MOS transistors and low voltage MOS transistors are mixedly mounted, a process is simplified and miniaturization thereof is achieved, without causing a parasitic transistor operation. An active region doped with a low impurity concentration of an impurity is formed in a channel region of a parasitic MOS transistor between two STI (shallow trench isolation) regions, and current flow between a source and a drain of the parasitic MOS transistor is cut off in a semiconductor device in which a high voltage MOS transistor and a microscopic low voltage MOS transistor are mixedly mounted on the same semiconductor substrate.

摘要翻译： 在混合安装高压MOS晶体管和低压MOS晶体管的半导体器件中，简化了工艺并实现了其小型化，而不会引起寄生晶体管的操作。 在两个STI（浅沟槽隔离）区域之间的寄生MOS晶体管的沟道区域中形成掺杂有杂质浓度低的有源区，并且将寄生MOS晶体管的源极与漏极之间的电流切断 在其中将高电压MOS晶体管和微观低电压MOS晶体管混合安装在同一半导体衬底上的半导体器件中。

公开(公告)号：US07939874B2

公开(公告)日：2011-05-10

申请号：US12012716

申请日：2008-02-05

申请人： Hitomi Sakurai

发明人： Hitomi Sakurai

IPC分类号： H01L27/108

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L27/0629 ,  H01L29/7881

摘要： A semiconductor device has semiconductor elements formed on a silicon substrate. A first one of the semiconductor elements has a region formed with a surface orientation of . A second one of the semiconductor elements has a region formed with a surface orientation of or . A third one of the semiconductor elements has a region formed with a surface orientation different from the respective surface orientations of the regions of the first and second semiconductor elements.

摘要翻译： 半导体器件具有形成在硅衬底上的半导体元件。 半导体元件中的第一个具有形成为具有<100>的表面取向的区域。 半导体元件中的第二个具有形成为具有<110>或<111>的表面取向的区域。 半导体元件中的第三个具有形成有与第一和第二半导体元件的区域的各个表面取向不同的表面取向的区域。

公开(公告)号：US20080197395A1

公开(公告)日：2008-08-21

申请号：US12012716

申请日：2008-02-05

申请人： Hitomi Sakurai

发明人： Hitomi Sakurai

IPC分类号： H01L29/94

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L27/0629 ,  H01L29/7881

摘要： In order to effectively miniaturize elements of a semiconductor device while improving the characteristics of each semiconductor element on a single chip of a silicon substrate or without impairing the characteristics, at least three different silicon surface directions are applied to the elements. Accordingly, at least the characteristics required for each element, on which the surface directions have influence, can be determined as the best characteristics.

摘要翻译： 为了有效地使半导体器件的元件小型化，同时改善硅衬底的单个芯片上的每个半导体元件的特性或不损害特性，至少三个不同的硅表面方向被施加到元件上。 因此，能够将表面方向所影响的各元件所需要的特性至少确定为最佳特性。