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公开(公告)号:US12119739B2
公开(公告)日:2024-10-15
申请号:US17853746
申请日:2022-06-29
Applicant: Navitas Semiconductor Limited
Inventor: Marco Giandalia , Jason Zhang , Hongwei Jia , Daniel M. Kinzer
CPC classification number: H02M1/08 , G05F1/573 , H02M1/32 , H02M3/155 , H02M3/158 , H03K3/012 , H02H9/02 , H03K2217/0081
Abstract: An electronic circuit is disclosed. The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, and a gate driver circuit including a pull-down transistor coupled to the gate terminal, and an input terminal arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal, where the gate driver circuit is arranged to store energy harvested from the input signal and use the stored energy to change a conductive state of the pull-down transistor. In one aspect, the transistor includes gallium nitride (GaN). In another aspect, the pull-down transistor includes GaN.
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公开(公告)号:US20230006657A1
公开(公告)日:2023-01-05
申请号:US17853740
申请日:2022-06-29
Applicant: Navitas Semiconductor Limited
Inventor: Hongwei Jia , Santosh Sharma , Daniel M. Kinzer , Victor Sinow , Matthew Anthony Topp
IPC: H03K3/012
Abstract: Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.
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公开(公告)号:US11855635B2
公开(公告)日:2023-12-26
申请号:US17853740
申请日:2022-06-29
Applicant: Navitas Semiconductor Limited
Inventor: Hongwei Jia , Santosh Sharma , Daniel M. Kinzer , Victor Sinow , Matthew Anthony Topp
IPC: H03K3/012
CPC classification number: H03K3/012
Abstract: Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.
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公开(公告)号:US11791709B2
公开(公告)日:2023-10-17
申请号:US17853749
申请日:2022-06-29
Applicant: Navitas Semiconductor Limited
Inventor: Marco Giandalia , Jason Zhang , Hongwei Jia , Daniel M. Kinzer
Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
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公开(公告)号:US20230006539A1
公开(公告)日:2023-01-05
申请号:US17853746
申请日:2022-06-29
Applicant: Navitas Semiconductor Limited
Inventor: Marco Giandalia , Jason Zhang , Hongwei Jia , Daniel M. Kinzer
Abstract: An electronic circuit is disclosed. The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, and a gate driver circuit including a pull-down transistor coupled to the gate terminal, and an input terminal arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal, where the gate driver circuit is arranged to store energy harvested from the input signal and use the stored energy to change a conductive state of the pull-down transistor. In one aspect, the transistor includes gallium nitride (GaN). In another aspect, the pull-down transistor includes GaN.
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公开(公告)号:US12261519B2
公开(公告)日:2025-03-25
申请号:US18463198
申请日:2023-09-07
Applicant: Navitas Semiconductor Limited
Inventor: Marco Giandalia , Jason Zhang , Hongwei Jia , Daniel M. Kinzer
Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
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公开(公告)号:US20230421046A1
公开(公告)日:2023-12-28
申请号:US18463198
申请日:2023-09-07
Applicant: Navitas Semiconductor Limited
Inventor: Marco Giandalia , Jason Zhang , Hongwei Jia , Daniel M. Kinzer
CPC classification number: H02M1/08 , H02M1/32 , H02M3/158 , H02M3/155 , H03K3/012 , G05F1/573 , H02H9/02
Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
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公开(公告)号:US20230006658A1
公开(公告)日:2023-01-05
申请号:US17853749
申请日:2022-06-29
Applicant: Navitas Semiconductor Limited
Inventor: Marco Giandalia , Jason Zhang , Hongwei Jia , Daniel M. Kinzer
Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
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