公开(公告)号：US20240195301A1

公开(公告)日：2024-06-13

申请号：US18488952

申请日：2023-10-17

Applicant: Navitas Semiconductor Limited

Inventor： Victor Sinow ,  Weijing Du

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/08 ,  H02M1/42

CPC classification number: H02M3/158 ,  H02M1/0009 ,  H02M1/08 ,  H02M1/4208

Abstract: Systems and methods that automatically detect state of switches in power converters are disclosed. In one aspect, a power switch includes a first switch coupled between a power input node and a first terminal of a load, a second switch coupled between the power input node and a second terminal of the load, first and second current sense devices arranged to transmit first and second signals including at least one of a magnitude and polarity of first and second currents through the first and second switches, respectively, a first driver circuit arranged to transmit first control signals to the first switch based at least in part on a voltage at the power input node and the first signal, and a second driver circuit arranged to transmit second control signals to the second switch based at least in part on the voltage at the power input node and the second signal.

公开(公告)号：US20230155503A1

公开(公告)日：2023-05-18

申请号：US18150600

申请日：2023-01-05

Applicant: Navitas Semiconductor Limited

Inventor： Victor Sinow ,  Weijing Du

IPC: H02M3/158 ,  H02M1/42 ,  H02M1/08 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M1/4208 ,  H02M1/08 ,  H02M1/0009

Abstract: Systems and methods that automatically detect state of switches in power converters are disclosed. In one aspect, a power switch includes a first switch coupled between a power input node and a first terminal of a load, a second switch coupled between the power input node and a second terminal of the load, first and second current sense devices arranged to transmit first and second signals including at least one of a magnitude and polarity of first and second currents through the first and second switches, respectively, a first driver circuit arranged to transmit first control signals to the first switch based at least in part on a voltage at the power input node and the first signal, and a second driver circuit arranged to transmit second control signals to the second switch based at least in part on the voltage at the power input node and the second signal.

公开(公告)号：US20230006657A1

公开(公告)日：2023-01-05

申请号：US17853740

申请日：2022-06-29

Applicant: Navitas Semiconductor Limited

Inventor： Hongwei Jia ,  Santosh Sharma ,  Daniel M. Kinzer ,  Victor Sinow ,  Matthew Anthony Topp

IPC: H03K3/012

Abstract: Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.

公开(公告)号：US20230006538A1

公开(公告)日：2023-01-05

申请号：US17853743

申请日：2022-06-29

Applicant: Navitas Semiconductor Limited

Inventor： Songming Zhou ,  Tao Liu ,  Ruixia Fei ,  Victor Sinow

IPC: H02M1/08 ,  H03K17/06 ,  H02M3/335 ,  H03K17/687 ,  H02M1/44

Abstract: Turn-off circuits. In one aspect, the turn-off circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, a first pull-down circuit connected to the gate terminal, a second pull-down circuit connected to the gate terminal, and a third pull-down circuit connected to the gate terminal. In another aspect, the first, the second and the third pull-down circuits are arranged to cause a turn off of the transistor by changing a voltage at the gate terminal at a first rate of voltage with respect to time from an on-state voltage to a first intermediate voltage, and from the first intermediate voltage to a second intermediate voltage at a second rate of voltage with respect to time, and from the second intermediate voltage to an off-state voltage at a third rate of voltage with respect to time, wherein the first rate is higher than the second rate.

公开(公告)号：US20240405764A1

公开(公告)日：2024-12-05

申请号：US18733480

申请日：2024-06-04

Applicant: Navitas Semiconductor Limited

Inventor： Nabil Akel ,  Jason Zhang ,  Victor Sinow ,  Thomas Ribarich

IPC: H03K17/10 ,  H02M1/08 ,  H03K17/081

Abstract: A circuit is disclosed. The circuit includes a gallium nitride (GaN) switch having a gate terminal, a drain terminal and a source terminal, a driver circuit having an output terminal coupled to the gate terminal, where the driver circuit is arranged to generate an output voltage at the output terminal such that: the output voltage is at a first voltage when a voltage at the drain terminal is below a predetermined voltage; the output voltage is at a second voltage when 1) the voltage at the drain terminal is above the predetermined voltage and 2) a time period during which the output voltage is at the second voltage is less than a predetermined time. In one aspect, the second voltage is greater than the first voltage.

公开(公告)号：US11594970B2

公开(公告)日：2023-02-28

申请号：US17575536

申请日：2022-01-13

Applicant: Navitas Semiconductor Limited

Inventor： Thomas Ribarich ,  Daniel M. Kinzer ,  Tao Liu ,  Marco Giandalia ,  Victor Sinow

IPC: G05F1/573 ,  G05F3/26 ,  H02M3/158 ,  H02M1/00

Abstract: A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.

公开(公告)号：US20250055371A1

公开(公告)日：2025-02-13

申请号：US18762523

申请日：2024-07-02

Applicant: Navitas Semiconductor Limited

Inventor： Victor Sinow

IPC: H02M3/158 ,  H02M1/00 ,  H03K17/687

Abstract: A method of operating a circuit is disclosed. The method includes providing an input terminal and a ground terminal coupled to a power supply, providing an output terminal and the ground terminal coupled to a load, providing a low-side circuit comprising a low-side power switch coupled between a switch node and the ground terminal, providing a high-side circuit comprising a high-side power switch coupled between the switch node and the output terminal, providing an inductor coupled between the switch node and the input terminal, detecting, by a controller, a valley of a voltage at the switch node, transmitting a signal, by the low-side circuit, to the high-side circuit in response to the controller detecting the valley, and turning on, by the high-side circuit, the high-side power switch for a time interval sufficient to generate a negative current in the inductor in response to receiving the signal.

公开(公告)号：US12126251B2

公开(公告)日：2024-10-22

申请号：US17853743

申请日：2022-06-29

Applicant: Navitas Semiconductor Limited

Inventor： Songming Zhou ,  Tao Liu ,  Ruixia Fei ,  Victor Sinow

IPC: H02M1/08 ,  H02M1/44 ,  H02M3/335 ,  H03K17/06 ,  H03K17/687

CPC classification number: H02M1/08 ,  H02M1/44 ,  H02M3/33507 ,  H03K17/06 ,  H03K17/687

Abstract: Turn-off circuits. In one aspect, the turn-off circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, a first pull-down circuit connected to the gate terminal, a second pull-down circuit connected to the gate terminal, and a third pull-down circuit connected to the gate terminal. In another aspect, the first, the second and the third pull-down circuits are arranged to cause a turn off of the transistor by changing a voltage at the gate terminal at a first rate of voltage with respect to time from an on-state voltage to a first intermediate voltage, and from the first intermediate voltage to a second intermediate voltage at a second rate of voltage with respect to time, and from the second intermediate voltage to an off-state voltage at a third rate of voltage with respect to time, wherein the first rate is higher than the second rate.

公开(公告)号：US11855635B2

公开(公告)日：2023-12-26

申请号：US17853740

申请日：2022-06-29

Applicant: Navitas Semiconductor Limited

Inventor： Hongwei Jia ,  Santosh Sharma ,  Daniel M. Kinzer ,  Victor Sinow ,  Matthew Anthony Topp

IPC: H03K3/012

CPC classification number: H03K3/012

Abstract: Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.

公开(公告)号：US20220231606A1

公开(公告)日：2022-07-21

申请号：US17575536

申请日：2022-01-13

Applicant: Navitas Semiconductor Limited

Inventor： Thomas Ribarich ,  Daniel M. Kinzer ,  Tao Liu ,  Marco Giandalia ,  Victor Sinow

IPC: H02M3/158 ,  H02M1/00

Abstract: A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.