公开(公告)号：US12119739B2

公开(公告)日：2024-10-15

申请号：US17853746

申请日：2022-06-29

Applicant: Navitas Semiconductor Limited

Inventor： Marco Giandalia ,  Jason Zhang ,  Hongwei Jia ,  Daniel M. Kinzer

IPC: H02M1/08 ,  G05F1/573 ,  H02M1/32 ,  H02M3/155 ,  H02M3/158 ,  H03K3/012 ,  H02H9/02

CPC classification number: H02M1/08 ,  G05F1/573 ,  H02M1/32 ,  H02M3/155 ,  H02M3/158 ,  H03K3/012 ,  H02H9/02 ,  H03K2217/0081

Abstract: An electronic circuit is disclosed. The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, and a gate driver circuit including a pull-down transistor coupled to the gate terminal, and an input terminal arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal, where the gate driver circuit is arranged to store energy harvested from the input signal and use the stored energy to change a conductive state of the pull-down transistor. In one aspect, the transistor includes gallium nitride (GaN). In another aspect, the pull-down transistor includes GaN.

公开(公告)号：US20220084978A1

公开(公告)日：2022-03-17

申请号：US17169320

申请日：2021-02-05

Applicant: NAVITAS SEMICONDUCTOR LIMITED

Inventor： Daniel M. Kinzer ,  Jason Zhang ,  Thomas Ribarich

IPC: H01L23/00 ,  H02M7/219 ,  H01L29/20 ,  H01L25/18 ,  H01L23/495

Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.

公开(公告)号：US11791709B2

公开(公告)日：2023-10-17

申请号：US17853749

申请日：2022-06-29

Applicant: Navitas Semiconductor Limited

Inventor： Marco Giandalia ,  Jason Zhang ,  Hongwei Jia ,  Daniel M. Kinzer

IPC: H02M1/32 ,  H02M1/08 ,  H02M3/158 ,  H02M3/155 ,  H03K3/012 ,  H02H9/02

CPC classification number: H02M1/08 ,  H02M1/32 ,  H02M3/155 ,  H02M3/158 ,  H03K3/012 ,  H02H9/02

Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.

公开(公告)号：US11715720B2

公开(公告)日：2023-08-01

申请号：US17169320

申请日：2021-02-05

Applicant: NAVITAS SEMICONDUCTOR LIMITED

Inventor： Daniel M. Kinzer ,  Jason Zhang ,  Thomas Ribarich

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/18 ,  H01L29/20 ,  H01L29/16 ,  H02M7/219

CPC classification number: H01L24/48 ,  H01L23/4951 ,  H01L23/49575 ,  H01L25/18 ,  H02M7/219 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/4807 ,  H01L2224/48229 ,  H01L2924/1425 ,  H01L2924/14252 ,  H01L2924/15333

Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.

公开(公告)号：US20230006539A1

公开(公告)日：2023-01-05

申请号：US17853746

申请日：2022-06-29

Applicant: Navitas Semiconductor Limited

Inventor： Marco Giandalia ,  Jason Zhang ,  Hongwei Jia ,  Daniel M. Kinzer

IPC: H02M1/08 ,  H02M3/158 ,  H02M1/32

Abstract: An electronic circuit is disclosed. The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, and a gate driver circuit including a pull-down transistor coupled to the gate terminal, and an input terminal arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal, where the gate driver circuit is arranged to store energy harvested from the input signal and use the stored energy to change a conductive state of the pull-down transistor. In one aspect, the transistor includes gallium nitride (GaN). In another aspect, the pull-down transistor includes GaN.

公开(公告)号：US12261519B2

公开(公告)日：2025-03-25

申请号：US18463198

申请日：2023-09-07

Applicant: Navitas Semiconductor Limited

Inventor： Marco Giandalia ,  Jason Zhang ,  Hongwei Jia ,  Daniel M. Kinzer

IPC: H02M3/155 ,  G05F1/573 ,  H02M1/08 ,  H02M1/32 ,  H02M3/158 ,  H03K3/012 ,  H02H9/02

Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.

公开(公告)号：US20240405764A1

公开(公告)日：2024-12-05

申请号：US18733480

申请日：2024-06-04

Applicant: Navitas Semiconductor Limited

Inventor： Nabil Akel ,  Jason Zhang ,  Victor Sinow ,  Thomas Ribarich

IPC: H03K17/10 ,  H02M1/08 ,  H03K17/081

Abstract: A circuit is disclosed. The circuit includes a gallium nitride (GaN) switch having a gate terminal, a drain terminal and a source terminal, a driver circuit having an output terminal coupled to the gate terminal, where the driver circuit is arranged to generate an output voltage at the output terminal such that: the output voltage is at a first voltage when a voltage at the drain terminal is below a predetermined voltage; the output voltage is at a second voltage when 1) the voltage at the drain terminal is above the predetermined voltage and 2) a time period during which the output voltage is at the second voltage is less than a predetermined time. In one aspect, the second voltage is greater than the first voltage.

公开(公告)号：US20230421046A1

公开(公告)日：2023-12-28

申请号：US18463198

申请日：2023-09-07

Applicant: Navitas Semiconductor Limited

Inventor： Marco Giandalia ,  Jason Zhang ,  Hongwei Jia ,  Daniel M. Kinzer

IPC: H02M1/08 ,  H02M1/32 ,  H02M3/158 ,  H02M3/155 ,  H03K3/012 ,  G05F1/573

CPC classification number: H02M1/08 ,  H02M1/32 ,  H02M3/158 ,  H02M3/155 ,  H03K3/012 ,  G05F1/573 ,  H02H9/02

Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.

公开(公告)号：US20230387067A1

公开(公告)日：2023-11-30

申请号：US18339123

申请日：2023-06-21

Applicant: Navitas Semiconductor Limited

Inventor： Daniel M. Kinzer ,  Jason Zhang ,  Thomas Ribarich

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/18 ,  H02M7/219

CPC classification number: H01L24/48 ,  H01L23/4951 ,  H01L23/49575 ,  H01L25/18 ,  H02M7/219 ,  H01L2924/1425 ,  H01L2924/15333 ,  H01L2224/48229 ,  H01L29/2003

Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.

公开(公告)号：US20230006658A1

公开(公告)日：2023-01-05

申请号：US17853749

申请日：2022-06-29

Applicant: Navitas Semiconductor Limited

Inventor： Marco Giandalia ,  Jason Zhang ,  Hongwei Jia ,  Daniel M. Kinzer

IPC: H03K3/012 ,  H02M3/155

Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.