-
公开(公告)号:US07913100B2
公开(公告)日:2011-03-22
申请号:US11906001
申请日:2007-09-29
申请人: Neil Songer , Seh W. Kwa , Jim Kardach , Darren Abramson
发明人: Neil Songer , Seh W. Kwa , Jim Kardach , Darren Abramson
IPC分类号: G06F1/32
CPC分类号: G06F1/3203 , G06F1/3253 , G06F1/3265 , G06F3/14 , G06F13/1668 , G09G2330/021 , Y02D10/151 , Y02D10/153
摘要: A method for trafficking data based at least in part on a power condition of a system resource. In one embodiment of the invention, a data trafficking device initiates data traffic in response to a detecting of an indication of the power condition. In another embodiment of the invention, the detected indication is independent of any data traffic of the data trafficking device.
摘要翻译: 至少部分地基于系统资源的功率状况来运送数据的方法。 在本发明的一个实施例中,数据传送装置响应于对功率状况的指示的检测而启动数据业务。 在本发明的另一个实施例中,检测到的指示独立于数据传送设备的任何数据业务。
-
公开(公告)号:US20090089606A1
公开(公告)日:2009-04-02
申请号:US11906001
申请日:2007-09-29
申请人: Neil Songer , Seh W. Kwa , Jim Kardach , Darren Abramson
发明人: Neil Songer , Seh W. Kwa , Jim Kardach , Darren Abramson
CPC分类号: G06F1/3203 , G06F1/3253 , G06F1/3265 , G06F3/14 , G06F13/1668 , G09G2330/021 , Y02D10/151 , Y02D10/153
摘要: A method for trafficking data based at least in part on a power condition of a system resource. In one embodiment of the invention, a data trafficking device initiates data traffic in response to a detecting of an indication of the power condition. In another embodiment of the invention, the detected indication is independent of any data traffic of the data trafficking device.
摘要翻译: 至少部分地基于系统资源的功率状况来运送数据的方法。 在本发明的一个实施例中,数据传送装置响应于对功率状况的指示的检测而启动数据业务。 在本发明的另一个实施例中,检测到的指示独立于数据传送设备的任何数据业务。
-
公开(公告)号:US20110047395A1
公开(公告)日:2011-02-24
申请号:US12916744
申请日:2010-11-01
申请人: Seh W. Kwa , Neil Songer , Jim Kardach , David J. Harriman
发明人: Seh W. Kwa , Neil Songer , Jim Kardach , David J. Harriman
CPC分类号: G06F1/3215 , G06F13/4221 , Y02D10/151
摘要: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.
摘要翻译: 在一些实施例中,可以利用主机芯片组心跳来在功率有效的基础上处理来自外部设备的中断。 主机芯片组心跳的可用性可以被发送到外部设备,并且那些外部设备可以将其活动的时间延长到不仅资源可用的时间段,而且活动的断言是有利的,因为主机芯片组已经从 降低功耗状态。
-
公开(公告)号:US20080244287A1
公开(公告)日:2008-10-02
申请号:US11729212
申请日:2007-03-28
申请人: Seh W. Kwa , Neil Songer , Jim Kardach , David J. Harriman
发明人: Seh W. Kwa , Neil Songer , Jim Kardach , David J. Harriman
IPC分类号: G06F1/32
CPC分类号: G06F1/3215 , G06F13/4221 , Y02D10/151
摘要: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.
摘要翻译: 在一些实施例中,可以利用主机芯片组心跳来在功率有效的基础上处理来自外部设备的中断。 主机芯片组心跳的可用性可以被发送到外部设备,并且那些外部设备可以将其活动的时间延长到不仅资源可用的时间段,而且活动的断言是有利的,因为主机芯片组已经从 降低功耗状态。
-
公开(公告)号:US08312304B2
公开(公告)日:2012-11-13
申请号:US12916744
申请日:2010-11-01
申请人: Seh W. Kwa , Neil Songer , Jim Kardach , David J. Harriman
发明人: Seh W. Kwa , Neil Songer , Jim Kardach , David J. Harriman
CPC分类号: G06F1/3215 , G06F13/4221 , Y02D10/151
摘要: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.
摘要翻译: 在一些实施例中,可以利用主机芯片组心跳来在功率有效的基础上处理来自外部设备的中断。 主机芯片组心跳的可用性可以被发送到外部设备,并且那些外部设备可以将其活动的时间延长到不仅资源可用的时间段,而且活动的断言是有利的,因为主机芯片组已经从 降低功耗状态。
-
公开(公告)号:US07831849B2
公开(公告)日:2010-11-09
申请号:US11729212
申请日:2007-03-28
申请人: Seh W. Kwa , Neil Songer , Jim Kardach , David J. Harriman
发明人: Seh W. Kwa , Neil Songer , Jim Kardach , David J. Harriman
CPC分类号: G06F1/3215 , G06F13/4221 , Y02D10/151
摘要: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.
摘要翻译: 在一些实施例中,可以利用主机芯片组心跳来在功率有效的基础上处理来自外部设备的中断。 主机芯片组心跳的可用性可以被发送到外部设备,并且那些外部设备可以将其活动的时间延长到不仅资源可用的时间段,而且活动的断言是有利的,因为主机芯片组已经从 降低功耗状态。
-
公开(公告)号:US20110302626A1
公开(公告)日:2011-12-08
申请号:US13213353
申请日:2011-08-19
申请人: Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
发明人: Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
IPC分类号: H04L29/06
CPC分类号: G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
-
公开(公告)号:US20110078473A1
公开(公告)日:2011-03-31
申请号:US12960277
申请日:2010-12-03
申请人: Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jevaseelan , Barnes Cooper , Nilesh V. Shah
发明人: Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jevaseelan , Barnes Cooper , Nilesh V. Shah
CPC分类号: G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
摘要翻译: 在一些实施例中,电子设备包括至少一个处理器,多个组件以及包括用于从电子设备中的一个或多个组件接收等待时间数据的逻辑的策略引擎,从等待时间数据计算最小等待时间容差值,以及 从最小延迟容限值确定电源管理策略。
-
公开(公告)号:US20090164818A1
公开(公告)日:2009-06-25
申请号:US11960417
申请日:2007-12-19
申请人: Seh W. Kwa , Neil Songer , James J. Walsh
发明人: Seh W. Kwa , Neil Songer , James J. Walsh
IPC分类号: G06F1/32
CPC分类号: G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要: Power management protocols for maximizing energy efficiency in power usage by mobile devices are described in this application. The power management protocols may allow for at least two power states by a CPU—active state, and inactive state. The active state corresponds to an active window when the mobile device is functional at full capacity and using the full clock speed frequency. The inactive state and opportunistic flush and fill states may be maximized by coordinating the activity of the CPU and other devices associated with a mobile device such as a bus, memory, graphics controller, hard drive, etc. By coordinating the critical functions of devices and CPU to occur during the active window, and delaying non-critical functions until an active window, the inactive and off states may be maximized, resulting in power savings and efficiency. Other embodiments are also described in this application.
摘要翻译: 在本应用中描述了用于最大化移动设备的能量使用能量的电力管理协议。 功率管理协议可以通过CPU活动状态和非活动状态允许至少两个功率状态。 活动状态对应于当移动设备在满容量功能并使用全时钟速度频率时的活动窗口。 通过协调CPU和与诸如总线,存储器,图形控制器,硬盘驱动器等移动设备相关联的其他设备的活动,可以最大化非活动状态和机会冲洗和填充状态。通过协调设备的关键功能和 CPU在活动窗口期间发生,并将非关键功能延迟到活动窗口,非活动和关闭状态可能最大化,从而节省电力并提高效率。 在本申请中还描述了其它实施例。
-
公开(公告)号:US20090172434A1
公开(公告)日:2009-07-02
申请号:US12006251
申请日:2007-12-31
申请人: Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
发明人: Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
CPC分类号: G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
摘要翻译: 在一些实施例中,电子设备包括至少一个处理器,多个组件以及包括用于从电子设备中的一个或多个组件接收等待时间数据的逻辑的策略引擎,从等待时间数据计算最小等待时间容差值,以及 从最小延迟容限值确定电源管理策略。
-
-
-
-
-
-
-
-
-