利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.024 秒)

    Frame attaching process
    1.
    发明申请
    Frame attaching process 审中-公开
    框架连接过程

    公开(公告)号：US20060079022A1

    公开(公告)日：2006-04-13

    申请号：US11280047

    申请日：2005-11-15

    申请人： Neng-Yu Tseng ,  Da-Shuang Kuan ,  Chia-Te Lin ,  Sheng-Lung Chen ,  Dylan Yu

    发明人： Neng-Yu Tseng ,  Da-Shuang Kuan ,  Chia-Te Lin ,  Sheng-Lung Chen ,  Dylan Yu

    IPC分类号： H01L21/48

    CPC分类号： H01L27/14683 ,  Y10T29/49126 ,  Y10T29/4913

    摘要： A frame attaching process is described. The frame attaching process is adapted for attaching a transparent substrate to an active area of a chip using a frame, wherein the active area of the chip has a functional area. In the frame attaching process, the frame can be formed on the attaching surface of the transparent substrate or on the active area of the chip. Then, the attaching surface of the transparent substrate is attached to the active area of the chip using the frame under a negative pressure. Finally, the frame is solidified. Therefore, in the frame attaching process, the possibility of frame cracking can be reduced and the yield of the frame attaching process can be improved.

    摘要翻译： 描述框架附接过程。 框架附接工艺适于使用框架将透明衬底附接到芯片的有源区域，其中芯片的有源区域具有功能区域。 在框架固定过程中，框架可以形成在透明基板的附着表面或芯片的有效区域上。 然后，使用框架在负压下将透明基板的安装面安装在芯片的有源区域上。 最后，框架固化。 因此，在框架固定过程中，可以减少框架破裂的可能性，并且可以提高框架附接过程的收益。

    Frame attaching process
    2.
    发明申请
    Frame attaching process 审中-公开
    框架连接过程

    公开(公告)号：US20050102827A1

    公开(公告)日：2005-05-19

    申请号：US10718455

    申请日：2003-11-19

    申请人： Neng-Yu Tseng ,  Da-Shuang Kuan ,  Chia-Te Lin ,  Sheng-Lung Chen ,  Dylan Yu

    发明人： Neng-Yu Tseng ,  Da-Shuang Kuan ,  Chia-Te Lin ,  Sheng-Lung Chen ,  Dylan Yu

    IPC分类号： H01L23/495 ,  H05K3/36

    CPC分类号： H01L27/14683 ,  Y10T29/49126 ,  Y10T29/4913

    摘要： A frame attaching process is described. The frame attaching process is adapted for attaching a transparent substrate to an active area of a chip using a frame, wherein the active area of the chip has a functional area. In the frame attaching process, the frame can be formed on the attaching surface of the transparent substrate or on the active area of the chip. Then, the attaching surface of the transparent substrate is attached to the active area of the chip using the frame under a negative pressure. Finally, the frame is solidified. Therefore, in the frame attaching process, the possibility of frame cracking can be reduced and the yield of the frame attaching process can be improved.

    摘要翻译： 描述框架附接过程。 框架附接工艺适于使用框架将透明衬底附接到芯片的有源区域，其中芯片的有源区域具有功能区域。 在框架固定过程中，框架可以形成在透明基板的附着表面或芯片的有效区域上。 然后，使用框架在负压下将透明基板的安装面安装在芯片的有源区域上。 最后，框架固化。 因此，在框架固定过程中，可以减少框架破裂的可能性，并且可以提高框架附接过程的收益。

    Method and structure for a wafer level packaging
    3.
    发明申请
    Method and structure for a wafer level packaging 有权
    晶圆级封装的方法和结构

    公开(公告)号：US20050077605A1

    公开(公告)日：2005-04-14

    申请号：US10986104

    申请日：2004-11-12

    申请人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

    发明人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

    IPC分类号： G02F1/13 ,  H01L21/48 ,  H01L21/50 ,  H01L23/00 ,  H01L23/02 ,  H01L23/28 ,  H01L27/14

    CPC分类号： H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/00014

    摘要： A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.

    摘要翻译： 提供了一种用于晶片级封装的方法和结构，其利用半导体晶片或透明基板上的多个间隔壁，其具有决定密封剂位置的能力。 结果，装置的尺寸由密封剂和间隔壁的位置决定，因此，在对整个半导体晶片进行模切工艺之后，缩小感光区和密封剂之间的距离将增加总模量 。 此外，半导体工艺决定间隔壁的高度，从而由于半导体晶片和透明基板之间的间隙的均匀性和密封剂的宽度将是 受控。

    Method and structure for a wafer level packaging
    4.
    发明授权
    Method and structure for a wafer level packaging 有权
    晶圆级封装的方法和结构

    公开(公告)号：US07087464B2

    公开(公告)日：2006-08-08

    申请号：US10986104

    申请日：2004-11-12

    申请人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

    发明人： Dylan Yu ,  Gary Guan ,  Jolas Chen ,  Yi-Ming Chang

    IPC分类号： H01L21/44

    CPC分类号： H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/00014

    摘要： A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.

    摘要翻译： 提供了一种用于晶片级封装的方法和结构，其利用半导体晶片或透明基板上的多个间隔壁，其具有决定密封剂位置的能力。 结果，装置的尺寸由密封剂和间隔壁的位置决定，因此，在对整个半导体晶片进行模切工艺之后，缩小感光区和密封剂之间的距离将增加总模量 。 此外，半导体工艺决定间隔壁的高度，从而由于半导体晶片和透明基板之间的间隙的均匀性和密封剂的宽度将是 受控。